TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 39

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3.5.1
is 1/fcgck [s].
can be used as the I/O ports.
(1)
(2)
(3)
Only the gear clock (fcgck) is used for the operation in the single-clock mode.
The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time
The gear clock (fcgck) is generated from the high-frequency clock (fc).
In the single-clock mode, the low-frequency clock generation circuit pins P02 (XTIN) and P03 (XTOUT)
Single-clock mode
clock (fcgck).
is released to the NORMAL1 mode.
after the interrupt processing is completed.
the IDLE1 mode activation instruction.
base timer.
become the same as the states when a reset is released. For operations of the peripheral circuits in the
IDLE0 mode, refer to the section of each peripheral circuit.
to the peripheral circuits except the time base timer.
is released, the timing generator starts the clock supply to all the peripheral circuits and the NORMAL1
mode is restored.
set after the NORMAL mode is restored.
the operation returns normal after the interrupt processing is completed.
In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck).
The NORMAL1 mode becomes active after reset release.
In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear
The IDLE1 mode is activated by setting SYSCR2<IDLE> to "1" in the NORMAL1 mode.
When the IDLE1 mode is activated, the CPU and the watchdog timer stop.
When the interrupt latch enabled by the interrupt enable register EFR becomes "1", the IDLE1 mode
When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal
When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows
In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time
In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or
The IDLE0 mode is activated by setting SYSCR2<TGHALT> to "1" in the NORMAL1 mode.
When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply
When the falling edge of the source clock selected at TBTCR<TBTCK> is detected, the IDLE0 mode
Note that the IDLE0 mode is activated and restarted, regardless of the setting of TBTCR<TBTEN>.
When the IDLE0 mode is activated with TBTCR<TBTEN> set at "1", the INTTBT interrupt latch is
When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "1",
NORMAL1 mode
IDLE1 mode
IDLE0 mode
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TMP89FS60