XC2VPX70 Xilinx, XC2VPX70 Datasheet
XC2VPX70
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XC2VPX70 Summary of contents
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... PROMs that © 2003-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
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... PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs. www.xilinx.com OE/RESET CEO Serial Interface ...
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... XC4VFX40 14,936,192 XC4VFX60 21,002,880 XC4VFX100 33,065,408 XC4VFX140 47,856,896 Virtex-4 SX XC4VSX25 9,147,648 XC4VSX35 13,700,288 XC4VSX55 22,749,184 Virtex-II Pro X XC2VPX20 8,214,560 XC2VPX70 26,098,976 Virtex-II Pro XC2VP2 1,305,376 XC2VP4 3,006,496 XC2VP7 4,485,408 XC2VP20 8,214,560 XC2VP30 11,589,920 XC2VP40 15,868,192 XC2VP50 19,021,344 XC2VP70 26,098,976 XC2VP100 34,292,768 DS123 (v2 ...
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... The XCF08P programming data sequence is delivered to the device XCF16P using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a XCF01S JTAG-compatible board tester simple microprocessor interface that emulates the JTAG instruction sequence. The ...
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... Each device meets all functional, performance, and data retention specifications within this endurance limit. Design Security The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via JTAG ...
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... XCFxxP this command also resets the selected design revision based on either the external EE 00EE REV_SEL[1:0] pins or on the internal design revision selection bits.) 13. IR[4] IR[3] ISC Status Security IR[6:5] IR[4] IR[3] ER/PROG ER/PROG ISC Status Error Status www.xilinx.com Instruction Description (1) IR[2] IR[1:0] → TDO IR[2] IR[1:0] → TDO DONE ...
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... PROM family code a = the specific Platform Flash PROM product the Xilinx manufacturer's ID The LSB of the IDCODE register is always read as logic 1 as defined by IEEE Std. 1149.1. USERCODE Register The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents ...
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... When BUSY is asserted High, the PROMs internal address counter stops incrementing, and the current data value is held on the data outputs. While BUSY is High, the PROM will continue driving the CLKOUT signal to the FPGA, clocking the FPGA’s configuration logic. www.xilinx.com T DOV DS026_04_020300 Figure 4 ...
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... Decompression The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a built-in data decompressor compatible with Xilinx advanced compression technology. Compressed Platform Flash PROM files are created from the target FPGA bitstream(s) using the iMPACT software. Only Slave Serial and Slave ...
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... FPGA’s bitstream. The bitstream is loaded into the FPGA either automatically upon power up command, depending on the state of the FPGA's mode pins. Xilinx Platform Flash PROMs are designed to download directly to the FPGA configuration interface. FPGA configuration modes which are supported by the XCFxxS Platform Flash PROMs include: Master Serial and Slave Serial ...
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... PROM byte by byte on pins [D0..D7], accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The bitstream data must be set up at the FPGA’s [D0..D7] input pins a short time before each rising edge of the FPGA's www.xilinx.com CC ("DC Characteristics Over 26). (Figure 7, 20) ...
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... For high-frequency parallel configuration, the BUSY pins of all PROMs are connected to the FPGA's BUSY output. This connection assures that the next data transition for the PROM is delayed until the FPGA is ready for the next configuration data byte. www.xilinx.com (Figure 10, CC ("DC Characteristics Over 26). ...
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... XCFxxP will sample the new design revision 16, Figure 11, page 19, selection before initiating the FPGA configuration 21). Multiple sequence. When using the XCFxxP Platform Flash PROM without design revisioning, if the CF pin is not connected to the FPGA PROG_B (or PROGRAM) pin, then the XCFxxP CF pin must be tied High. www.xilinx.com 13 ...
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... For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP not connected to PROGB, then it must be tied to V DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS (2) V CCO (1) D0 DIN MODE PINS Xilinx FPGA Master Serial CLK CCLK CE DONE CEO INIT_B (3) CF PROG_B ...
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... For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. XCFxxP not connected to PROGB, then it must be tied to V DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS (2) V CCO (1) D0 DIN MODE PINS Xilinx FPGA Slave Serial (3) CLK CCLK CE DONE CEO INIT_B (4) CF ...
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... CF TDI TMS TCK TDO GND via a 4.7 kΩ pull-up resistor. CCO www.xilinx.com (1) (1) DIN MODE PINS DOUT DIN Xilinx FPGA Xilinx FPGA Master Serial Slave Serial CCLK CCLK DONE DONE INIT_B INIT_B PROG_B PROG_B TDI TDO TDI TMS TMS TCK ...
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... For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP not connected to PROGB, then it must be tied to V via a 4.7 kΩ pull-up resistor. CCO Figure 9: Configuring in Master SelectMAP Mode DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS (2) V CCO (1) D[0:7] D[0:7] MODE PINS Xilinx FPGA Master SelectMAP CLK CCLK CE DONE CEO INIT_B (5) CF PROG_B (4) (4) BUSY ...
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... For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP not connected to PROGB, then it must be tied to V via a 4.7 kΩ pull-up resistor. CCO DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS (2) V CCO (1) D[0:7] D[0:7] MODE PINS Xilinx FPGA Slave SelectMAP (5) CLK CCLK CE DONE CEO INIT_B (6) CF PROG_B (4) ...
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... BUSY TDI TMS TCK TDO GND www.xilinx.com (1) D[0:7] MODE PINS D[0:7] MODE PINS (3) I/O (3) RDWR_B I/O RDWR_B CS_B Xilinx FPGA Xilinx FPGA Master SelectMAP Slave SelectMAP CCLK CCLK DONE DONE INIT_B INIT_B PROG_B PROG_B (4) (4) BUSY BUSY TDO TDI TDI TMS TMS TCK TCK ...
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... TDO EN_EXT_SEL REV_SEL[1:0] GND . CCO For the XCFxxP not connected to PROGB, then it www.xilinx.com (1) DIN MODE PINS MODE PINS DOUT DIN Xilinx FPGA Xilinx FPGA Slave Serial Slave Serial CCLK CCLK DONE DONE INIT_B INIT_B PROG_B PROG_B TDI TDI TMS TMS ...
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... BUSY TDI TMS TCK TDO EN_EXT_SEL REV_SEL[1:0] GND . CCO www.xilinx.com (1) D[0:7] MODE PINS D[0:7] MODE PINS RDWR_B (3) I/O CS_B Xilinx FPGA Xilinx FPGA Slave SelectMAP Slave SelectMAP CCLK CCLK DONE DONE INIT_B INIT_B PROG_B PROG_B (4) (4) BUSY BUSY TDI TDO TDI TMS TMS TCK ...
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... TDO must not be pulled Low, and TCK must be stopped (High or Low). When using the FPGA DONE signal to drive the PROM CE pin High to reduce standby power after configuration, an external pull-up resistor should be used. Typically a 330Ω www.xilinx.com Figure 14, page 22. to rise above CCINT ...
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... Low address = EA (3) : don't change Else If address = TC (2) : don't change Unchanged High (4) X (1) Reset (4) X Held reset (4) X Held reset www.xilinx.com Outputs DATA CEO Active High Active High-Z Low Reduced High-Z High Active High-Z High Standby Outputs DATA CEO CLKOUT Active ...
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... XCF08P, XCF16P, XCF04S XCF32P –0.5 to +4.0 –0.5 to +2.7 –0.5 to +4.0 –0.5 to +4.0 –0.5 to +4.0 –0.5 to +4.0 –0.5 to +3.6 –0.5 to +3.6 –0.5 to +5.5 –0.5 to +3.6 –0.5 to +3.6 –0.5 to +3.6 –0.5 to +5.5 –0.5 to +3.6 –65 to +150 –65 to +150 +125 +125 www.xilinx.com. XCF08P, XCF16P, XCF04S XCF32P Max Min Max 50 0.2 50 – 0 – 0.5 – 10 Units V V ...
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... V – – 2.0 – 1.7 – 70% V – CCO – – (1) – – 500 0 – V –40 – and 90 CCO CCO Description www.xilinx.com XCF08P, XCF16P, XCF32P Min Typ Max 3.6 1.65 1.8 2.0 3.6 3.0 3.3 3.6 2.7 2.3 2.5 2.7 1.9 1.7 1.8 1.9 – TBD 1.5 TBD 3.6 3.0 3.3 3.6 2.7 2.3 2.5 2.7 0.8 0 – 0.8 0.7 0 – 0.7 – – ...
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... IN V CCINT V – – – GND V IN – 1.0 MHz f = 1.0 MHz V = GND V IN – 1.0 MHz f = 1.0 MHz www.xilinx.com XCF08P, XCF16P, XCF32P Units Test Min Max = –4 mA 2.4 – V – –500 µA CCO V – 0.4 V – CCO = –50 µA V – 0.4 = TBD TBD – ...
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... CAC XCF01S, XCF02S, Min 300 (9) 300 (9) (8) (8) (6) when V = 3.3V or 2.5V CCO (6) when V = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO CF (8) CF www.xilinx.com T HCE T HOE SXT HXT T T SRV HRV XCF08P, XCF16P, XCF04S XCF32P Max Min Max 300 300 – – – ...
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... CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO (3) (3) (5) (5) (6) (6) (8) = 3.3V or 2.5V CCO (8) = 1.8V CCO (8) = 3.3V or 2.5V CCO (8) = 1.8V CCO (8) (8) (8) www.xilinx.com XCF08P, XCF16P, XCF04S XCF32P Min Max Min – 25 – – 30 – 30 – – 25 – – 30 – – – – – ...
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... XCF01S, XCF02S, Min – (8) – = 0.0V and V = 3.0V FPGA Data setup time. Example: With the XCF32P in serial mode with V CYC CAC = ns. CYC www.xilinx.com XCF08P, XCF16P, XCF04S XCF32P Max Min Max – 300 – – 300 – minimum. HCF ...
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... CCO = 3.3V or 2.5V CCO = 1.8V CCO (2) when V = 3.3V or 2.5V CCO (2) when V = 1.8V CCO (2) when V = 3.3V or 2.5V CCO (2) when V = 1.8V CCO (2) when V = 3.3V or 2.5V CCO (2) when V = 1.8V CCO www.xilinx.com T HCE T HOE T DDC T CECF T OECF T EOH SXT HXT T T SRV HRV XCF08P, XCF16P, XCF32P Min Max 300 300 – TBD – ...
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... CCO = 3.3V or 2.5V CCO = 1.8V CCO (9) = 3.3V or 2.5V CCO (9) = 1.8V CCO = 3.3V or 2.5V with decompression CCO = 1.8V with decompression CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V with decompression CCO = 1.8V with decompression CCO CCO CCO www.xilinx.com XCF08P, XCF16P, XCF32P Min 2000 2000 = 3.3V or 2.5V 2000 CCO = 1.8V 2000 CCO – – ...
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... CCO = 3.3V or 2.5V CCO = 1.8V CCO = 0.0V and V = 3.0V FPGA Data setup time. Example: With the XCF32P in serial mode with V CYCO CCDD = ns. CYCO www.xilinx.com XCF08P, XCF16P, XCF32P Min Max 300 – 300 – 300 – 300 – 300 – 300 – ...
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... CCO (2) when V = 1.8V CCO (2) when V = 3.3V or 2.5V CCO (2) when V = 1.8V CCO (2) when V = 3.3V or 2.5V CCO (2) when V = 1.8V CCO (5) when V = 3.3V or 2.5V CCO (5) when V = 1.8V CCO www.xilinx.com T HCE T HOE T DDC T CECF T OECF T EOH SXT HXT T T SRV HRV XCF08P, XCF16P, XCF32P Min Max 300 300 – TBD – ...
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... CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V with decompression CCO (11) = 1.8V with decompression CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO = 3.3V or 2.5V CCO = 1.8V CCO (9) (11) www.xilinx.com XCF08P, XCF16P, XCF32P Min Max = 3.3V or 2.5V 2000 – = 1.8V 2000 – 12 – 12 – 8 – 8 – TBD 0 TBD – ...
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... CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ pull- CCO 12. When JTAG CONFIG command is issued, PROM will drive CF Low for at least the T DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS Description (10) (11) = 0.0V and V = 3.0V www.xilinx.com XCF08P, XCF16P, XCF32P Min Max 12 12.5 minimum. HCF Units MHz MHz ...
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... CCO = 1.8V – CCO (3) when V = 2.5V or 3.3V – CCO (3) when V = 1.8V – CCO = 2.5V or 3.3V – CCO = 1.8V – CCO – = 1.8V – CCO = 0.0V and V = 3.0V www.xilinx.com First Bit T OCE T OOE ds123_23_102203 XCF08P, XCF16P, XCF04S XCF32P Max Min Max 25 – – – – – – ...
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... JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50 KΩ resistive pull- system if the pin is not driven. +3.3V Supply. Positive 3.3V supply voltage for internal logic. www.xilinx.com 20-pin TSSOP (VO20/VOG20) to provide a logic 1 to the CCJ ...
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... TDO output voltage driver and TCK, TMS, and TDI input buffers. Ground Do not connect. (These pins must be left unconnected.) 20 VCCJ 19 VCCO 18 VCCINT 17 TDO 16 (DNC) 15 (DNC) 14 (DNC) 13 CEO 12 (DNC) 11 GND ds123_02_071304 www.xilinx.com 20-pin TSSOP (VO20/VOG20 12, 14, 15 ...
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... D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. D0-D7 are the DATA output pins to provide parallel data for configuring a Xilinx FPGA in SelectMap (parallel) mode. The D0 output is set to a high-impedance state during ISPEN (when not clamped). The D1-D7 outputs are set to a high-impedance state during ISPEN (when not clamped) and when serial mode is selected for configuration ...
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... JTAG Serial Data Output. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50KΩ resistive pull- provide a logic 1 to the CCJ system if the pin is not driven. +1.8V Supply. Positive 1.8V supply voltage for internal logic. www.xilinx.com 48-pin 48-pin TSOP TFBGA (VO48/ (FS48/ ...
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... JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply voltage connected to the TDO output voltage driver and TCK, TMS, and TDI input buffers. Ground Do Not Connect. (These pins must be left unconnected.) VO48/VOG48 Top View www.xilinx.com 48-pin 48-pin TSOP TFBGA (VO48/ (FS48/ VOG48) FSG48) 8, 30, ...
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... XCFxxP FS48/FSG48 Pinout Diagram Pin Name VCCINT TMS DNC A B DNC TDO E GND F DNC G DNC H DNC GND GND Figure 17: FS48/FSG48 Pinout Diagram (Top View) TDI DNC REV_SEL0 REV_SEL1 VCCO VCCINT GND VCCJ TCK EN_EXT_SEL D1 D0 www.xilinx.com FS48/FSG48 Top View ds121_01_071604 42 ...
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... DS123 (v2.9) May 09, 2006 Platform Flash In-System Programmable Configuration PROMS XCF04S VO20 C XCF32P FS48 C Operating Range/Processing XCF08PFS48 C XCF01SVOG20 C XCF16PFS48 C XCF02SVOG20 C XCF32PFS48 C XCF04SVOG20 C XCF04S-V www.xilinx.com Operating Range/Processing –40°C to +85° –40°C to +85°C) A XCF08PVOG48 C XCF08PFSG48 C XCF16PVOG48 C XCF16PFSG48 C XCF32PVOG48 C XCF32PFSG48 C ...
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... R Revision History The following table shows the revision history for this document. Date Version 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • • • • Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to section 12/15/03 2.2 • Added paragraph to section • ...
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... Page LC HC ♦ New rows added for T and T CEC OEC Figure 7, page 15, Figure 12, page page 41 "Internal Oscillator," page 8 "CLKOUT," page 8 description www.xilinx.com 24: Removed parameter T from table. (T SOL into two separate columns CKMIN1 CKMIN 25: Separated V and V CCO 26: 27 ...
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... XCFxxP. Figure 2, page 2 updated to show clock source muxing and route clocking to all functional blocks. Table 2, page "VIL" maximum for 2.5V operation in "Recommended Operating Conditions," page 25 to match LVCMOS25 standard. www.xilinx.com 5. 6. 15, Figure 8, page 16, Figure 9, page 20, and Figure 13, page 21 updated to specify the 8 ...