XC2VPX70 Xilinx, XC2VPX70 Datasheet - Page 46

• Manufacturer Part Number: XC2VPX70
• Description: (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: Xilinx

DS123 (v2.9) May 09, 2006
12/29/05
05/09/06
R
2.8
2.9
• Update to the first paragraph of
• Added JTAG cautionary note to
• Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under
• Sections
• Notes for
• Enhanced description under section
• Enhanced description on design revision sampling under section
• Figure 4 and Figure 5 renamed to
• Value for
• Block diagram in
• Added Virtex-5 LX support to
•
Instruction Register (16 bits wide)," page
Source," page
Source," page 30
Source," page 33
page
need for a pull-up resistor if CF is not connected to PROGB.
figures, and table and figure references renumber this point forward.
functional blocks.
"VIL"
to match LVCMOS25 standard.
18,
maximum for 2.5V operation in
"XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock
Figure 11, page
Figure 6, page
"ICCINT," page 26
27,
Figure 2, page 2
and
added to
"XCFxxP PROM as Configuration Master with CLK Input Pin as Clock
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
"XCFxxP PROM as Configuration Master with Internal Oscillator as Clock
14,
19,
"AC Characteristics Over Operating Conditions," page
Figure 7, page
updated from 5mA to 1mA for XCFxxP.
Figure 12, page
Table 2, page
"IEEE 1149.1 Boundary-Scan (JTAG)," page
Page
updated to show clock source muxing and route clocking to all
Table 7, page 6
"CLKOUT," page
"Recommended Operating Conditions," page 25
5.
6.
15,
3.
20, and
Figure 8, page
and
Figure 13, page 21
8.
Table 8, page 6
16,
"Design Revisioning," page
Figure 9, page
respectively. All tables,
updated to specify the
5.
17,
27.
Figure 10,
"XCFxxP
updated
9.
46