XC2VPX70 Xilinx, XC2VPX70 Datasheet - Page 8

• Manufacturer Part Number: XC2VPX70
• Description: (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: Xilinx

TAP AC Parameters
Table 10
Table 10: Test Access Port Timing Parameters
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
an optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled when programming
the PROM, and the oscillator can be set to either the default
frequency or to a slower frequency
Configuration Master with Internal Oscillator as Clock
Source," page
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
the programmable option to enable the CLKOUT signal
which allows the PROM to provide a source synchronous
clock aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources: the
CLK input pin or the internal oscillator. The input clock source
is selected during the PROM programming sequence.
Output data is available on the rising edge of CLKOUT.
DS123 (v2.9) May 09, 2006
T
T
T
T
T
T
CKMIN
MSS
MSH
DIS
DIH
DOV
Symbol
shows the timing parameters for the TAP waveforms shown in
TCK
TDO
TMS
TDI
R
33).
TCK minimum clock period when V
TMS setup time when V
TMS hold time when V
TDI setup time when V
TDI hold time when V
TDO valid delay when V
T
CKMIN
("XCFxxP PROM as
T
DIS
T
CCJ
MSS
CCJ
CCJ
CCJ
CCJ
Figure 4: Test Access Port Timing
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
Description
CCJ
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
= 2.5V or 3.3V
T
DIH
T
MSH
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. On CE
rising edge transition, if OE/RESET is High and the PROM
terminal count has not been reached, then CLKOUT
remains active for an additional eights clock cycles before
being disabled. On a OE/RESET falling edge transition,
CLKOUT is immediately disabled. When disabled, the
CLKOUT pin is put into a high-impedance state and should
be pulled High externally to provide a known state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and drives the CEO pin enabling the next
PROM in the PROM chain. The next PROM will begin
driving the CLKOUT signal once that PROM is enabled and
data is available for transfer.
During high-speed parallel configuration without
compression, the FPGA drives the BUSY signal on the
configuration interface. When BUSY is asserted High, the
PROMs internal address counter stops incrementing, and
the current data value is held on the data outputs. While
BUSY is High, the PROM will continue driving the CLKOUT
signal to the FPGA, clocking the FPGA’s configuration logic.
Figure
T
DOV
4.
Min
100
10
25
10
25
–
DS026_04_020300
Max
30
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
8