MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 14

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

MAS 3507D
2.7.4.2. Mode 2:32 Bit/Sample (Inverted SOI)
If the serial output generates 32 bits per audio sample,
only the first 20 bits will carry valid audio data. The 12
trailing bits are set to zero by default (see Fig. 2–7)
The 12 trailing bits for left and right channel of the SDO
interface can be accessed by writing to registers as
shown in Table 2–7.
Table 2–7: Access for Trailing Bits
SOC
SOD
SOI
Fig. 2–7: Schematic timing of the SDO interface in 32 bit/sample mode
14
Register
$c5
$c6
V
V
V
V
V
V
h
l
h
l
h
l
31 30 29 28 27 26 25
left 32-bit audio sample
Bit 0 ... 11
Left Channel
Right Channel
...
...
7 6 5 4 3 2 1 0
31
30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0
2.7.4.3. Other Output Modes
The interface is also configurable by software to work
in different modes. It is possible to choose:
– 16 or 32 bit/sample modes,
– inverted or noninverted word strobe (SOI),
– no delay or delay of data related to word strobe
– inverted or noninverted I
For further details see Section 3.7.2.2.
right 32-bit audio sample
...
PRELIMINARY DATA SHEET
2
S-Clock (SOC).
Micronas