MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 42

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

MAS 3507D
42
34
35
36
37
38
39
40
41
42
43
44
PMQFP
44-pin
32
33
1)
2)
Start-up configuration see Section 2.8.
Not available in PIO-DMA mode, see Section 2.8.1.
Pin No.
PLCC
44-pin
19
18
17
16
15
14
13
12
11
10
9
8
7
PBGA
49-ball
B7
A7
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
A1
Pin Name
Test Alias in ()
SIC
PI4
PI3
PI2
PI1
PI0
CLKO
PUP
WSEN
WRDY
AVDD
CLKI
AVSS
(PI5)
Type
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
SUPPLY
IN
SUPPLY
Connection
(If not used)
X
X
X
X
X
X
LV
LV
X
LV
VDD
X
VSS
Short Description
Serial Input Clock
Start-up
mode
Operation
Start-up
Enable Layer 3 / Disable Layer 3
decoding
Operation
(Sampling frequency)
Start-up
Enable Layer 2 / Disable Layer 2
decoding
Operation
(Sampling frequency)
Start-up
SDO: Select 32-bit mode / 16-bit I
mode
Operation
(Emphasis)
Start-up
Select Multimedia mode / Broadcast
mode
Operation
(Emphasis)
Clock Output for the D/A converter
Power Up, i.e. status of voltage super-
vision
Enable DSP and Start DC/DC Con-
verter
If WSEN = 0: valid clock input at CLKI
If WSEN = 1: clock synthesizer PLL
locked
Supply for analog circuits
Clock input
Ground supply for analog circuits
1)
1)
1)
1)
1)
PRELIMINARY DATA SHEET
: Select SDI / PIO-DMA input
:
:
:
:
2)
2)
2)
2)
2)
: MPEG-Frame Sync
: MPEG header bit 20
: MPEG header bit 21
: MPEG header bit 30
: MPEG header bit 31
Micronas
2
S