MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 43

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

PRELIMINARY DATA SHEET
4.2.1. Pin Descriptions
4.2.1.1. Power Supply Pins
Connection of all power supply pins is mandatory for
the function of the MAS 3507D.
VDD
VSS
The VDD/VSS pair is internally connected with all digi-
tal modules of the MAS 3507D.
XVDD
XVSS
The XVDD/XVSS pins are internally connected with
the pin output buffers.
AVDD
AVSS
The AVDD/AVSS pair is connected internally with the
analog blocks of the MAS 3507D, i.e. clock synthesizer
and supply voltage supervision circuits.
4.2.1.2. DC/DC Converter Pins
DCEN
The DCEN input signal enables the DC/DC converter
operation.
DCSG
The DC converter Signal Ground pin is used as a
basepoint for the internal switching transistor of the
DC/DC converter. It must always be connected to
ground.
DCSO
DCSO is an open drain output and should be con-
nected with external circuitry (inductor/diode) to start
the DC/DC converter. When the DC/DC converter is
not used, it has to be connected to VSS.
VSENS
The VSENS pin is the input for the DC/DC converter
feedback loop. It must be connected directly with the
Schottky diode and the capacitor as shown in Fig. 2–3.
When the DC/DC converter is not used, it has to be
connected to VDD.
Micronas
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
OUT
IN
IN
4.2.1.3. Control Lines
I2CC
I2CD
Standard I
resistors tied from each line to VDD.
4.2.1.4. Parallel Interface Lines
4.2.1.4.1. PIO Handshake Lines
PIO handshake lines are not used during start-up but
in operation mode. Read out of the status information
and the demand mode work in P-mode: set PCS = ’0’
and PR = ’1’. Usage of PIO-DMA mode is possible
with input mode via PIO.
PCS
The PIO chip select must be set to ‘0’ to activate the
PIO as Output in operation mode (e.g. PI19 = demand
signal in mutimedia mode & SDI input mode).
PR
The PIO PR must be set to ‘1’ to validate data output
from MAS 3507D.
RTW
RTW is not supported by the built-in firmware.
RTR
RTR is only supported by the built-in firmware in PIO-
DMA input mode.
EOD
End of DMA (EOD) is only supported by the built-in
firmware in PIO-DMA input mode.
4.2.1.4.2. PIO Data Lines
The function of the parallel interface is separated into
two parts. During start-up, the PIO will read the start-
up configuration (independent from the PIO hand-
shake lines). This is done to define the environment for
the MAS 3507D (see Section 2.8.1. for details).
After start-up, the PIO will be switched to P-mode.
With the PR = ‘1’ and the PCS = ‘0’, the PIO interface
is defined as output and displays some status informa-
tion of the MPEG decoder. The PIO can be connected
to an external controller or to a display unit (e.g. LED).
The internal MPEG decoder firmware attaches specific
functions to the following pins:
2
C control lines. Normally there are Pullup-
SDA
SCL
MAS 3507D
IN/OUT
IN/OUT
OUT
OUT
OUT
43
IN
IN