MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 44

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

MAS 3507D
PI19
When MAS 3507D is in multimedia mode it demands
with PI19 = ’1’ for new input data.
PI18
PI17
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
PI16
PI15
PI14
The SIC*, SID*, and SII* may be configured as alterna-
tive serial input lines in order to support alternative
serial digital inputs.
PI13
PI12
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
PI8
The MPEG-CRC-ERROR pin is activated if no suc-
cessful MPEG decoding is possible. The reason might
be that the CRC check of the MPEG Frame header
has detected an error or that no valid bit stream is
available. The error signal will stay active for the entire
duration of one MPEG frame.
During start-up, this pin is an input for enabling/dis-
abling the CLKO+divider (see Section 3.6.).
PI4
The MPEG-FRAME-SYNC signal indicates that a
MPEG header has been decoded properly and the
internal MPEG decoder is in a synched state. The
MPEG-FRAME-SYNC signal is inactive after Power
On Reset and will be activated if a valid MPEG Layer 2
or 3 header has been recognized. The signal will be
cleared if the ancillary data information is read out by
the controller via I
During start-up, this pin sets either SDI- or PIO-DMA-
input mode (see Section 3.6.).
PI3
PI2
PI1
PI0
These pins mirror the according bits of the MPEG
header (see Table 2–9 for details).
During start-up, these pins are input pins (see
Section 3.6.).
44
SAMPLING FREQUENCY
SAMPLING FREQUENCY
MPEG-FRAME-SYNC
MPEG-CRC-ERROR
2
C interface.
DEMAND PIN
MPEG-IDEX
EMPHASIS
EMPHASIS
LAYER ID
LAYER ID
MPEG-ID
(SIC*)
(SII*)
(SID*
OUT/IN
OUT/IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
4.2.1.5. Voltage Supervision And Other Functions
CLKI
This is the clock input of the MAS 3507D. CLKI should
be a buffered output of a crystal oscillator. Standard
clock frequency is 14.725. Others can be used, if
PLL_offset register is changed by I
CLKO
The CLKO is an oversampling clock that is synchro-
nized to the digital audio data (SOD) and the frame
identification (SOI).
PUP
The PUP output indicates that the power supply volt-
age exceeds its minimal level (software adjustable).
WSEN
WSEN enables DSP operation and starts DC/DC-con-
verter.
WRDY
WRDY has two functions depending on the state of the
WSEN signal.
If WSEN = ’0’, it indicates that a valid clock has been
recognized at the CLKI clock input.
If WSEN = ’1’, the WRDY output will be set to ‘0’ until
the internal clock synthesizer has locked to the incom-
ing audio data stream, and thus, the CLKO clock out-
put signal is valid.
4.2.1.6. Serial Input Interface
SID
SII
SIC
Data, Frame Indication, and Clock line of the serial
input interface. The SII line should be connected with
VSS in the standard mode.
4.2.1.7. Serial Output Interface
SOD
SOI
SOC
Data, Frame Indication, and Clock line of the serial out-
put interface. The SOI indicates whether the left or the
right audio sample is transmitted. Besides the two
modes (selected by the PI1 during start-up), it is possi-
ble to reconfigure the interface.
PRELIMINARY DATA SHEET
2
C.
Micronas
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN