MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 19

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

PRELIMINARY DATA SHEET
Note: S =
I2C_DA
I2C_CL
Fig. 3–1: I
3.2. Command Structure
The I
via the I
syntax.
MAS 3507D during its normal operation without any
loss or interruption of the incoming data or outgoing
audio data stream. These I
controller to access internal states, RAM contents,
internal hardware control registers, and even a down-
load of an alternative software module. The command
structure
MAS 3507D. The registers of the MAS 3507D are
either general purpose, e.g. for program flow control,
or specialized registers that directly affect hardware
blocks. The unrestricted access to these registers
allows the system controller to overrule the firmware
configuration of the serial interfaces or the default input
line selection.
The control interface is also used for low bit rate data
transmission, e.g. MPEG-embedded ancillary data
transmission. The data information is performed by
sending a ‘read memory ’ command to the MAS 3507D
and by reading the memory block that temporarily con-
tains the required information. The synchronization
between the controller and the MAS 3507D is done via
a MPEG-FRAME-SYNC signal or by monitoring the
MPEGFrameCount register (at the cost of a higher
work load for the controller).
The MAS 3507D firmware scans the I
odically and checks for pending or new commands.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms. Table 3–4 shows the basic con-
troller
MAS 3507D.
Micronas
2
C control of the MAS 3507D is done completely
P =
ACK =
NAK =
Wait =
2
commands
C data register by using a special command
The
2
C bus protocol (MSB first; data must be stable while clock is high)
allows
S
I
I
Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate ‘End of Read’
I
Acknowledge-Bit: LOW on I2C_DA from slave or master
commands
2
2
2
C-Bus Start Condition from master
C-Bus Stop Condition from master
C-Clock line is held low, while the MAS 3507D is processing the I
sophisticated
that
are
2
are
C commands allow the
available
executed
control
2
C interface peri-
1
0
by
by
of
the
the
the
3.2.1. The Internal Fixed Point Number Format
Internal register or memory values can easily be
accessed via the I
number representations are used: the fixed point nota-
tion ‘v’ and the 2’s complement number notation ‘r’.
The conversion between the two forms of notation is
easily done (see the following equations).
r = v x 524288.0 + 0.5; ( 1.0
v = r / 524288.0; ( 524288 < r < 524287)
P
2
C interface. In this document, two
2
C command.
v < 1.0)
MAS 3507D
(EQ 1)
(EQ 2)
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