MAS3507D Micronas Intermetall, MAS3507D Datasheet - Page 41

• Manufacturer Part Number: MAS3507D
• Description: Mpeg 1/2 Layer 2/3 Audio Decoder
• Manufacturer: Micronas Intermetall

PRELIMINARY DATA SHEET
Micronas
PMQFP
44-pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin No.
PLCC
44-pin
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PBGA
49-ball
F4
G3
E4
G4
F5
G5
F6
G6
E5
E6
F7
D6
E7
D7
C6
C7
B6
Pin Name
Test Alias in ()
PCS
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
SOC
PI8
XVDD
XVSS
SID
SII
(PI11)
(PI10)
(PI9)
(PI7)
(PI6)
Type
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
OUT
OUT
OUT
IN
OUT
SUPPLY
SUPPLY
IN
IN
LV
LV
X
X
Connection
(If not used)
X
LV
LV
LV
LV
LV
LV
LV
LV
LV
X
X
VSS
Short Description
PIO Chip Select, Active Low
PIO Data [19]
1. Demand Pin in SDI mode
2. data bit [7], MSB (PIO-DMA input
mode)
PIO Data [18]
1. MPEG header bit 11
(SDI mode)
2. data bit [6] (PIO-DMA input mode)
PIO Data [17]
1. MPEG header bit 12 – MPEG ID
(SDI mode)
2. data bit [5] (PIO-DMA input mode)
PIO Data [16]
1. SIC*, alternative input for SIC (SDI
mode)
2. data bit [4] (PIO-DMA input mode)
PIO Data [15]
1. SII*, alternative input for SII (SDI
mode)
2. data bit [3] (PIO-DMA input mode)
PIO Data [14]
1. SID*, alternative input for SID (SDI
mode)
2. data bit [2] (PIO-DMA input mode)
PIO Data [13]
1. MPEG header bit 13 – Layer ID (SDI
mode)
2. data bit [1] (PIO-DMA input mode)
PIO Data [12]
1. MPEG header bit 14 – Layer ID (SDI
mode)
2. data bit [0] (PIO-DMA input mode)
Serial Output Data
Serial Output Frame Identification
Serial Output Clock
Start-up
Operation
Positive Supply of Output Buffers
Ground of Output Buffers
Serial Input Data
Serial Input Frame Identification
1)
: Clock output scaler on / off
2)
: MPEG CRC error
MAS 3507D
MPEG ID
41