CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet
CS8952T-CQ
Related parts for CS8952T-CQ
CS8952T-CQ Summary of contents
Page 1
... IEEE 802.3 Auto-Negotiation with Next Page Support ! Six LED drivers (LNK, COL, FDX, TX, RX, and SPD) ! Low power (135 mA Typical) CMOS design operates on a single 5 V supply ORDERING INFORMATION CS8952T- °C 100-pin TQFP CS8952T-IQ - °C 100-pin TQFP CDB8952 Evaluation Board ...
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... MII Management Frame Structure .........................................................................................27 CONFIGURATION ....................................................................................................................... 29 Configuration At Power-up/Reset Time ..................................................................................29 Configuration Via Control Pins ...............................................................................................29 Configuration via the MII ........................................................................................................ 29 CS8952T REGISTERS ................................................................................................................. 30 Basic Mode Control Register - Address 00h .......................................................................... 31 Basic Mode Status Register - Address 01h ........................................................................... 33 PHY Identifier Register, Part 1 - Address 02h ........................................................................ 35 PHY Identifier Register, Part 2 - Address 03h ........................................................................ 36 Auto-Negotiation Advertisement Register - Address 04h ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Clocking Schemes .................................................................................................................63 Recommended Magnetics .....................................................................................................64 Power Supply and Decoupling ...............................................................................................64 General Layout Recommendations ........................................................................................64 SPECIFICATIONS AND CHARACTERISTICS ...........................................................................67 ABSOLUTE MAXIMUM RATINGS..........................................................................................67 RECOMMENDED OPERATING CONDITIONS .....................................................................67 QUARTZ CRYSTAL REQUIREMENTS..................................................................................67 DC CHARACTERISTICS ........................................................................................................68 DC CHARACTERISTICS (CONT.) .........................................................................................69 SWITCHING CHARACTERISTICS.........................................................................................70 MECHANICAL SPECIFICATIONS ..............................................................................................82 Package Dimensions .............................................................................................................82 Recommended PCB Footprint ...
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... To support 10BASE-T appli- cations, the CS8952T provides a 10BASE-T serial port (Seven-wire ENDEC interface). Typical Connection Diagram Figure 1 illustrates a typical MII to CS8952T appli- cation with twisted-pair interfaces. Refer to the De- sign Considerations information on power supply requirements and de- coupling, crystal and magnetics requirements, and twisted-pair transceiver connections ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver VDD_MII 4.7K 1.5K 4.7K MDIO MDC 4 TXD[3:0] TX_ER/TXD[4] TX_EN 33 TX_CLK 33 RXD[0] 33 RXD[1]/PHYAD[1] 33 RXD[2] 33 RXD[3]/PHYAD[3] 33 RX_ER/RXD[4]/PHYAD[4] 33 RX_DV/MII_DRV 33 RX_CLK 33 COL/PHYAD0 33 CRS/PHYAD[2] VDD_MII 4.7K RX_EN MII_IRQ LPSTRT PWRDN REPEATER BP4B5B BPALIGN LPBK ISODEF 10BT_SER RESET XTAL_I 25MHz XTAL_O ...
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... RESET 16 REPEATER 17 CLK25 18 VSS 19 VDD 20 VSS 21 VDD_MII 22 VSS 23 10BT_SER 24 TEST1 25 TEST0 CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 6 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver CS8952 100-pin TQFP ( mm) CS8952T 75 RSVD 74 RSVD 73 LED5 72 LED4 71 LED3 70 LED2 69 LED1 68 SPD10 67 SPD100 66 VDD_MII 65 VSS 64 PWRDN 63 ISODEF 62 ...
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... Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This clock may be asynchronous to RX_CLK and TX_CLK. MDIO - Management Data Input/Output. Bi-Directional, Pin 27. Bi-directional signal used to transfer management data between the CS8952T and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1 ...
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... When RX_DV is low and RXD[3:0] = “1110”, RX_ER high indicates a False Carrier condition. CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 8 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 10BT_SER pin Nominal frequency n/a 25 MHz low (parallel) 2.5 MHz high (serial) 10 MHz CS8952T series resistor. For DS206TPP2 ...
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... IEEE802.3u specification, the external series resistors may not be necessary. TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42. Continuous clock signal used by the CS8952T as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power- reset. ...
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... TX_EN must be pulled up to VDD_MII. TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38. When high, TX_ER indicates to the CS8952T that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952T will ignore the data on the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place Mb/s mode, TX_ER has no effect on the transmitted data ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57. These three-level input pins are sampled during power-up or reset. They control the forced or advertised auto-negotiation operating modes. If either of these pins is left unconnected, internal logic pulls its signal to a mid-range value, designated as 'M' in the following table. Either pin may also be connected MHz TTL-level clock source, designated as ’ ...
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... LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 12 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver pull-up or pull-down resistor. pull-up or pull-down resistor. pull-up or pull-down resistor. CS8952T DS206TPP2 ...
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... LPBK - Loopback Enable. Input, Pin 51. When this pin is asserted high and the CS8952T is operating in 100 Mb/s mode, the CS8952T will perform a local loopback inside the PMD block. The loopback includes all CS8952T 100 Mb/s functionality except the MLT-3 coders and the analog line interface blocks. ...
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... LED to indicate 10 Mb/s operation. SPD100 - 100 Mb/s Speed Indication. Output, Pin 67. This pin is asserted high when the CS8952T is configured for 100 Mb/s operation. This pin can be used to drive a low-current LED to indicate 100 Mb/s operation. TCM - Transmit Clock Mode Initialization. Input, Pin 59. ...
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... General Pins CLK25 - 25 MHz Clock. Tristate Output, Pin 17 MHz Clock is output on this pin when the CS8952T is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes ...
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... RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99. These seven pins are reserved and should be tied to VSS. VDD_MII - I/O Pad Power. Pins 21, 34, and 66. These pins provide power to all CS8952T digital I/O pads. Typically VDD_MII will be either +5V or +3.3V. VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100. ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver FUNCTIONAL DESCRIPTION Digital System Interface The primary digital interface to the CS8952T is an enhanced IEEE 802.3 Media Independent Interface (MII). The MII supports parallel data transfer, ac- cess to the CS8952T Control and Status registers, and several status and control pins. ...
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... IDLE (Note 3) 0101 First Start of Stream Symbol 0101 Second Start of Stream Symbol 0000 First End of Stream Symbol 0000 Second End of Stream Symbol Table 2. 4B5B Symbol Encoding/Decoding CS8952T Comments DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Name 5-bit Symbol CONTROL (Note 1) I 11111 J 11000 K 10001 T 01101 R 00111 CODE VIOLATIONS H 00100 V0 00000 0110 or 0101 (Note 2) V1 00001 0110 or 0101 (Note 2) V2 00010 0110 or 0101 (Note 2) V3 00011 0110 or 0101 (Note 2) V4 ...
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... Loopback, Bypass, and Receiver Error Mask Reg- ister (address 18h). BP4B5B can be selected by set- ting bit 14 of the same register. Pin BPALIGN causes more of the CS8952T to be bypassed than the BP4B5B pin. BPALIGN also bypasses the scrambler/descrambler (see Figure 1). Asserting the REPEATER pin or setting bit 12 in ...
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... The false carrier detection logic described earlier is used to increment a false carrier counter. When two consecutive false carrier events are detected, the CS8952T will deassert the Link OK bit in the Self Status Register (address 19h), set the Link Status Change bit in the Interrupt Status Register (address ...
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... Configuration Register (ad- dress 1Ch) is clear, the CS8952T automatically corrects a reversal. SQE (Heartbeat) Test Function When SQE is enabled, the CS8952T will assert the COL pin for approximately 10 bit times within 1 s after the transmission of each packet. The SQE function is disabled by default when the REPEATER pin is deasserted on reset or power- up ...
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... Burst yields a Link Code Word which identifies the capability of the remote device. In order to support legacy 10 and 100 Mb/s devic- es, the CS8952T also supports parallel detection. In parallel detection, the CS8952T monitors activity on the media to determine the capability of the link partner even without auto-negotiation having oc- curred ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 6) Analog circuitry is reset and recalibrated when- ever the CS8952T changes between 10 Mb/s and 100 Mb/s modes. After a reset, the CS8952T latches the signals on various input pins in order to initialize key registers and goes through a self configuration. This in- cludes calibrating on-chip analog circuitry. Time required for the reset calibration is typically 40 ms ...
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... DEF signals. The MII_IRQ pin provides an inter- rupt signal to the controller when a change of state has occurred in the CS8952T, eliminating the need for the system to poll the CS8952T for state chang- es. The RX_EN signal allows the receiver outputs to be electrically isolated. The ISODEF pin con- ...
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... Figure 3 illustrates reception with errors. MII Transmit Data TX_EN is used by the MAC to signal to the CS8952T that valid nibbles of data are being pre- sented across the MII via TXD[3:0]. TX_EN must be asserted synchronously with the first nibble of preamble, and must remain asserted as long as val- id data is being presented to the MII ...
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... MDIO pulled to a logic ONE. At the beginning of each transaction, the MAC will typically send a sequence of 32 contiguous logic ONE bits on MDIO with 32 corresponding clock cycles on MDC to provide the CS8952T with a pat- tern that it can use to establish synchronization. Optionally, the CS8952T may be configured to op- Data ...
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... For a read transaction, the MAC should tri-state the MDIO pin beginning on the first bit time, and the CS8952T will begin driving the MDIO signal to a logic ZERO during the second bit time. During write transactions, ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver CONFIGURATION The CS8952T can be configured in a variety of ways. All control and status information can be ac- cessed via the MII Serial Management Interface. Additionally, many configuration options can be set at power-up or reset times via individual control lines ...
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... CS8952T REGISTERS The CS8952T register set is comprised of the 16- bit status and control registers described below. A detailed description each register follows. Register Address 0h Basic Mode Control Register 1h Basic Mode Status Register 2h PHY Identifier #1 3h PHY Identifier #2 4h Auto-Negotiation Advertisement Register 5h Auto-Negotiation Link Partner Ability Register ...
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... Clearing this reset to 0 bit disables auto-negotiation. When this bit is set, the CS8952T enters a low power consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... When set, the COL pin will be asserted within 10 bit times in response to the assertion of TX_EN. Upon the deassertion of TX_EN, COL will be deasserted within 4 bit times. When Collision Test is clear, COL functions normally. 000 0000 CS8952T DESCRIPTION DS206TPP2 ...
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... Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 1 When this bit is set, it indicates that the CS8952T is capable of 10BASE-T Half-Duplex operation. This bit reflects the status of the 10BASE-T/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver RESET 1 This bit indicates that the CS8952T has auto-negotia- tion capability. It will always read back a value When set, this bit indicates that a valid link has been established. Upon a link failure, this bit is cleared and latched ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver PHY Identifier Register, Part 1 - Address 02h BIT NAME TYPE 15:0 Organizationally Read/Write 001Ah Unique Identifier (bits 3:18) CIRRUS LOGIC ADVANCED PRODUCT DATABOOK DS206TPP2 Organizationally Unique Identifier: Bits[3:10 Organizationally Unique Identifier: Bits[11:18] RESET This identifier is assigned to PHY manufacturers by the IEEE ...
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... National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. These bits indicate the CS8952T part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Setting this bit will signal to the link partner that a fault condition has occurred. This field determines the advertised capabilities of dependent on the the CS8952T as shown below. When the bit is set, status of the the corresponding technology will be advertised dur- AN[1:0] pins (See ing auto-negotiation ...
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... When set, this bit indicates that the link partner is capable of participating in the Next Page exchange. 0 When set, this bit indicates that the link partner has received consistent data from the CS8952T. 0 This bit indicates that a fault condition occurred on the far end. When this bit is set and auto-negotiation is enabled, the Remote Fault bit in the Basic Mode Status Register (address 01h) will also be set ...
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... When set, this bit indicates that the link partner is capable of Next Page exchange. 1 This bit is a status bit which indicates to the Manage- ment Layer that the CS8952T supports Next Page capability. 0 When set, this bit indicates that a valid word of auto- negotiation data has been received and its integrity verified ...
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... Configuration Register (address 1Ch) is set. When set, this bit indicates to the link partner that the CS8952T can comply with the last received mes- sage. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Configuration Register (address 1Ch) is set. When set, an interrupt will be generated each time the CS8952T detects a change in the link status. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set ...
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... Configuration Register (address 1Ch) is set. When set, an interrupt will be generated when a Jab- ber condition is detected by the 10BASE-T MAU. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952T DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Interrupt Mask Register - Address 10h (Cont.) BIT NAME TYPE 5 Auto-Neg Complete Read/Write 0 4 Parallel Detection Read/Write 0 Fault 3 Parallel Fail Read/Write 0 2 Remote Fault Read/Write 0 1 Page Received Read/Write 0 0 Reserved Read Only CIRRUS LOGIC ADVANCED PRODUCT DATABOOK ...
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... FCCR may be read before saturat- ing. 0 This bit is set when the MSB of the Receive Error Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over. CS8952T Remote FCCR RECR Loopback ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Interrupt Status Register - Address 11h (Cont.) BIT NAME TYPE 8 Remote Loopback Read Only Fault 7 Reset Complete Read Only 6 Jabber Detect Read Only 5 Auto-Neg Complete Read Only 4 Parallel Detection Read Only Fault 3 Parallel Fail Read Only ...
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... The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h). 0 CS8952T DESCRIPTION DS206TPP2 ...
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... Disconnect Counter Read/Write 0000h CIRRUS LOGIC ADVANCED PRODUCT DATABOOK DS206TPP2 Disconnect Counter Disconnect Counter RESET This field contains a count of the number of times the CS8952T has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h DESCRIPTION 47 ...
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... False Carrier Counter RESET 0000h This field contains a count of the number of times the CS8952T has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delimiter (SSD). The counter is incremented at the end of such events to prevent multiple increments. This counter is cleared upon readout and will saturate at FFFFh. ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Scrambler Key Initialization Register - Address 14h 15 14 Load 7 6 BIT NAME TYPE 15 Load Read/Set 14:11 Reserved Read Only 10:0 Scrambler Initializa- Read/Write Reset value is tion Key CIRRUS LOGIC ADVANCED PRODUCT DATABOOK DS206TPP2 Reserved Scrambler Initialization Key ...
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... Receive Error Counter Receive Error Counter RESET 0000h This counter increments for each packet in which one or more receive errors is detected that is not due to a collision event. This counter is cleared upon readout and will roll-over to 0000h. CS8952T DESCRIPTION DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Descrambler Key Initialization Register - Address 16h 15 14 Load 7 6 BIT NAME TYPE 15 Load Read/Set 14:11 Reserved Read Only 10:0 Descrambler Initial- Read/Write Reset value is ization Key CIRRUS LOGIC ADVANCED PRODUCT DATABOOK DS206TPP2 Reserved Descrambler Initialization Key ...
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... When set, this bit unlocks certain read only control registers for factory testing. Leave clear for proper operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952T Preamble Unlock Regs Fast Test ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver PCS Sub-Layer Configuration Register - Address 17h (Cont.) BIT NAME TYPE 9 MF Preamble Read/Write 0 Enable 8 Fast Test Read/Write 0 7 CLK25 Disable Read/Write When TCM pin is 6 Enable LT/100 Read/Write 1 5 CIM Disable Read/Write Reset to the logic ...
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... When set, this bit will reset all digital logic and regis- ters to their initial values. The analog circuitry will not be affected. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. CS8952T DS206TPP2 ...
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... If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952T does not detect carrier, and thus will not report bad SSD events. When set, this bit causes the receive 5B4B decoder on the BP4B5B and the transmit 4B5B encoder to be bypassed ...
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... When set, this bit causes code errors to be reported by a value RXD[3:0] and the assertion of RX_ER. When clear, this bit causes code errors to be reported by a value RXD[3:0] and the assertion of RX_ER. This bit is superseded by the Code Error Report Enable bit. CS8952T DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.) BIT NAME TYPE 3 Premature End Read/Write 0 Error Report Select 2 Link Error Report Read/Write 0 Enable 1 Packet Error Report Read/Write 0 Enable 0 Code Error Report Read/Write 0 Enable ...
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... This bit may be used to determine the current status of the link. 0 When high, this bit indicates that the CS8952T low power state. 0 This bit is high whenever the CS8952T is receiving valid data direct copy of the state of the RX_DV pin accessible by software ...
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... These bits define the PHY PHYAD[4:0] pins. address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952T’s registers individually via the MDIO and MDC pins. DESCRIPTION 59 ...
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... Polarity Disable bit. When set, this bit selects 10BASE-T serial mode. on the 10BT_SER When low, this bit selects 10BASE-T nibble mode. pin. This bit will only affect the CS8952T if it has been configured for 10 Mb/s operation. 0 0000 0000 CS8952T 10 9 ...
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... Mb/s operation with auto-negotiation enabled, the CS8952T will go into 10 Mb/s mode. If operating in 100 Mb/s mode with no auto-negotiation, then clearing this bit has no effect. When set, and if the CS8952T is in half-duplex mode, inverse of the this bit enables the 10BASE-T SQE function. When value on the the part is in repeater mode, this bit is cleared and REPEATER pin ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver RESET DESCRIPTION When set, the jabber function is enabled. When clear, and if the CS8952T is in 10BASE-T full-duplex or 10BASE-T ENDEC loopback mode, the jabber func- tion is disabled. Note: When the National Compatibility Mode bit (bit 7) is set, the Jabber function may also be disabled for 10BASE-T half-duplex, although this is not recom- mended ...
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... CS8952T and should be placed as close as possible to RES pin. Connect the other end of this resistor directly to the ground plane. Connect the adjacent CS8952T ground pins (pins 85 and 87) to the grounded end of the resistor forming a “shield” around the RES connection. CS8952 Figure 7 ...
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... V. Component Crystal Transformer Table 10. Support Component Manufacturers Each CS8952T power pin should be connected to a 0.1 µF bypass capacitor and then to the power plane. The bypass capacitors should be located as close to its corresponding power pin as possible. Connect ground pins directly to the ground plane. General Layout Recommendations ...
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... RJ45 and the primary (chip) side facing the analog side (pins 76-100) of CS8952T. Place the CS8952T in turn as close possible. • Use the bottom layer for signal routing as a sec- ond choice. You may place all components on the top layer ...
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... Table 11. RJ-45 Wiring nations close to the load. • Locate the crystal as close to the CS8952T as possible, running short traces on the compo- nent side in order to reduce parasitic load ca- pacitance. • Add bulk capacitance at each connector where power may be supplied. For example, MII pow- er may be provided at the MII connector and at a separate connector for test purposes ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SPECIFICATIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) Parameter Power Supply Input Current Input Voltage Output Voltage Ambient Temperature Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. ...
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... I DDSLPUP V -0.3 IXH V 3.0 IXH I -40 IXL I IXH 39.996 IXC t 18 IXL 4.0mA 10.0mA 4.0mA OL = 43.0mA OL = 26.0mA 4.0mA OL CS8952T Typ Max - 135 145 - 900 - - 900 - - 0 0 40.004 - ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver DC CHARACTERISTICS (CONT.) Parameter Digital I/O (cont.) Output High Voltage CLK25, SPD10, SPD100 Output High Voltage (MII_DRV = 1) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK V = 5V; I DD_MII V = 3.3V, I DD_MII Output High Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], ...
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... CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 70 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Symbol Min Typ V 2 300 - ISQ V 125 - SQL V 0. SYM Z - 100 OUT t 3 RFS DCD 400 0 CS8952T Max Unit 2.8 V 525 mV 290 mV 1.05 V 102 % - ohms 5.0 ns 0.5 ns +/-0 1400 ps 1 p-p 1000 s 350 s DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter 10BASE-T Serial Mode Transmit Timing TX_CLK Period TX_CLK Pulse Width Transmit Data Setup to TX_CLK Transmit Data Hold from TX_CLK Transmit Throughput Delay TX+/- Pair Jitter into 100 Load TX+/- Pair Positive Hold Time at End of Packet ...
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... RCOLA t - RCOLD t - RCP RCH RCL t 35 RCRSH t 6 RCYC t - RLAT t 35 RDS t 50 RDH t t RXJ RCRSD t RCOLD t t RCP RCSRH t t RCH t RCL RDS CS8952T Typ Max Unit - +/-13 600 ns - 400 ns - 600 ns - 400 ns 100 - 250 RCYC t ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter 10Base-T Jabber/Unjabber Timing Maximum Transmit Time Unjabber Time TX_EN TX+/TX- COL Parameter 10Base-T SQE (Heartbeat) Timing COL (SQE) Delay after TX_EN off COL (SQE) Pulse Width TX_CLK t TES TX_EN COL CIRRUS LOGIC ADVANCED PRODUCT DATABOOK ...
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... LCDW t 111 LCCW t - FLW t 15 LPP LN1 t - LN4 t 50 LN5 t 50 LN6 Data Pulse t LPW t LCDW t LCCW t FLW t LPP t LPW CS8952T Typ Max 100 130 64 69.5 128 139 150 Clock Pulse DS206TPP2 Unit ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter 100BASE-X MII Receive Timing “Start of Stream” to CRS asserted “End of Stream” to CRS de-asserted “Start of Stream” to COL asserted “End of Stream” to COL de-asserted RX_CLK Period RX_CLK Pulse Width "Start of Stream" to RXD latency ...
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... CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 76 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Symbol Min t - TCP TCL, TCH t 10 TDS t 0 TDH t - TCRSA t - TCRSD Aligned t 6 TPD - t TDH t TPD CS8952T Typ Max Unit TCP In/Out t t TCL TCH ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter 10BASE-T MII Receive Timing RX+/- preamble to CRS asserted RX+/- end of packet to CRS de-asserted RX+/- preamble to COL asserted RX+/- end of packet to COL de-asserted RX_CLK Period RX_CLK Pulse Width "Start of Stream" to RXD latency RXD[3:0], RX_ER, RX_DV setup to rising edge of ...
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... CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 78 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Symbol Min t - TCP TCL, TCH t 10 TDS t 0 TDH t 0 TCRSA t 0 TCRSD t 6 TPD t 250 TXH t - TXOFF t TDH CS8952T Typ Max Unit 400 - ns 200 - 4 TCP In/Out t t ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter 10BASE-T Serial Receive Timing Allowable receive jitter at bit cell center RX+/- active to CRS active CRS de-asserted after RX+/- inactive RX+/- active to COL active COL de-asserted after RX+/- inactive RX_CLK Period RX_CLK Pulse Width CSR hold from RX_CLK ...
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... CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Symbol Min Typ t - 400 TCP 200 TCL, TCH TDS TDH TPD TPD t 250 - TXH TXOFF t TCP t TCH t TDH t TXJ CS8952T Max Unit - 500 ns +/- 4.5 s In/Out t TCL TXH Out t TXOFF DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver SWITCHING CHARACTERISTICS (CONT.) Parameter Serial Management Interface MDC Period MDC Pulse Width MDIO Setup to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO valid (MDIO as output) MDC t MDIS MDIO (Input) MDIO (Output) ...
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... MECHANICAL SPECIFICATIONS Package Dimensions DIM (Note Nominal pin pitch is 0.50 mm. CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 82 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Min Max - 1.60 0.05 0.15 0.17 0.27 15.70 16.30 13.90 14.10 15.70 16.30 13.90 14.10 0.40 0.60 0.45 0.75 0.00 7.00 CS8952T A A1 Unit degrees DS206TPP2 ...
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... CS8952T CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Recommended PCB Footprint D Y DIM CIRRUS LOGIC ADVANCED PRODUCT DATABOOK DS206TPP2 Min Typ Max - 15.40 - 12.00 - 0.50 13.80 - 14.00 0.30 - 0.40 - 1.60 16.80 - 17. Unit - ...
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... Added typical PCB footprint in mechanical section. - Changed XTAL_I electrical specification to reflect the fact it is referenced to VDD instead of VDD_MII. - Added more verbiage to Functional Description. CIRRUS LOGIC ADVANCED PRODUCT DATABOOK 84 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver Changes and V exception lists CS8952T DS206TPP2 ...
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Notes • ...
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