CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet - Page 27

• Manufacturer Part Number: CS8952T-CQ
• Description: 100BASE E-X AND 10BASE-T TRANSCEIVER
• Manufacturer: Cirrus Logic

Transmit errors should be signaled by the MAC by
asserting TX_ER for one or more TX_CLK cycles.
TX_ER must be synchronous with TX_CLK. This
will cause the CS8952T to replace the nibble with
a HALT symbol in the frame being transmitted.
This invalid data will be detected by the receiving
PHY and flagged as a bad frame. Figure 4 illus-
trates transmission without errors, and Figure 5 il-
lustrates transmission with errors.
MII Management Interface
The CS8952T provides an enhanced IEEE 802.3
MII Management Interface. The interface consists
of three signals: a bi-directional serial data line
(MDIO), a data clock (MDC), and an optional in-
terrupt signal (MII_IRQ). The Management Inter-
face can be used to access status and control
registers internal to the CS8952T. The CS8952T
implements an extended set of 16-bit MII registers.
Eight of the registers are defined by the IEEE 802.3
specification, while the remaining registers provide
enhanced monitoring and control capabilities.
DS206TPP2
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
TXD[3:0]
TXD[3:0]
TX_CLK
TX_CLK
TX_EN
TX_ER
TX_EN
TX_ER
Preamble
Preamble
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
Figure 4. Transmission without errors
Figure 5. Transmission with errors
Data
Data
Data
Data
Data
Data
As many as 31 devices may share a single Manage-
ment Interface. A unique five-bit PHY address is
associated with each device, with all devices re-
sponding to PHY address 00000. The CS8952T de-
termines its PHY address at power-up or reset
through the PHYAD[4:0] pins.
MII Management Frame Structure
Frames transmitted through the MII Management
Interface have the format shown in Table 6 on
page 28.
When the management interface is idle, the MDIO
signal will be tri-stated, and the MAC is required to
keep MDIO pulled to a logic ONE.
At the beginning of each transaction, the MAC will
typically send a sequence of 32 contiguous logic
ONE bits on MDIO with 32 corresponding clock
cycles on MDC to provide the CS8952T with a pat-
tern that it can use to establish synchronization.
Optionally, the CS8952T may be configured to op-
Data
Data
Data
XX
Data
Data
CRC
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