CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet - Page 65

• Manufacturer Part Number: CS8952T-CQ
• Description: 100BASE E-X AND 10BASE-T TRANSCEIVER
• Manufacturer: Cirrus Logic

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DS206TPP2
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Layer 4: (bottom) Second choice signal rout-
Place transformer T1 as close to the RJ45 connec-
tor as possible with the secondary (network) side
facing the RJ45 and the primary (chip) side facing
the analog side (pins 76-100) of CS8952T. Place
the CS8952T in turn as close to T1 as possible.
Use the bottom layer for signal routing as a sec-
ond choice. You may place all components on
the top layer. However, bypass capacitors are
optimally placed as close to the chip as possible
and may be best located underneath the
CS8952T on the bottom layer. Termination
components at the RJ-45 and fiber transceiver
may also be optimally placed on the bottom
layer.
Connect a 0.1 F bypass capacitor to each
CS8952T VDD and VDD_MII pin. Place it as
close to its corresponding power pin as possible
and connect the other lead directly to the
ground plane.
The 4.99K reference resistor should be placed
as close to the RES pin as possible. Connect the
other end of this resistor to the ground plane us-
ing a via. Connect the adjacent VSS pins (pins
85 and 87) to the grounded end of the resistor
forming a shield as illustrated in Figure 7.
Controlled impedance is necessary for critical
signals TX+/- and RX+/-. These should be run
as microstrip transmission lines (100
ential, 50
should be 68
(For short MII signal paths one may standard-
ize on a given trace width for all traces without
significant degradation in signal integrity.)
ing, bypass components
single-ended). The MII signals
microstrip transmission lines.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
differ-
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Avoid routing traces other than the TX and RX
signals under transformer T1 and the RJ45 con-
nector. Signals may run on the bottom side un-
derneath the CS8952T as long as they stay
away from critical analog traces.
Connect all CS8952T ground and power pins
directly to the ground and power planes, re-
spectively. Note: The VDD_MII power pins
may need their own power plane or plane seg-
ment in +3.3 V MII applications.
Depending on the orientation and location of
the transformer, the CS8952T, and the RJ-45,
and on whether the application is for a NIC or a
switch, the RX and TX pairs may need to cross.
This should be done by changing layers on a
pair by pair basis only, using the minimum
number of vias, and making sure that each trace
within a pair “sees” the same path as its peer.
Figure 6 shows the CS8952T in a NIC or adapt-
er configuration. It may be configured for a hub
or repeater application by changing the wiring
to the RJ-45 as shown in Table 11.
Differential pair transmission lines should be
routed close together (one trace width spacing
edge-to-edge) and kept at least two trace widths
away from other traces, components, etc. TX
and RX pairs should be routed away from each
other and may use opposite sides of the PCB as
necessary, Each member of the differential pair
should “see” the same PCB terrain as its peer.
Unused spaces on the signal layers should be
filled with ground fill (pour). Vias should con-
nect the ground patches to the ground plane.
This is especially recommended (symmetrical-
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