CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet - Page 15

• Manufacturer Part Number: CS8952T-CQ
• Description: 100BASE E-X AND 10BASE-T TRANSCEIVER
• Manufacturer: Cirrus Logic

TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
Media Interface Pins
RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
General Pins
CLK25 - 25 MHz Clock. Tristate Output, Pin 17.
RES - Reference Resistor. Input, Pin 86.
DS206TPP2
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
These three-level pins allow adjustment to the rise and fall times of the 100BASE-TX
transmitter output waveform. The rise and fall times are symmetric.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer
primary.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer
primary.
A 25 MHz Clock is output on this pin when the CS8952T is configured to use an external
reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the
Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating
modes.
CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-
layer Configuration Register (address 17h).
This input should be connected to ground with a 4.99 k
needed for the biasing of internal analog circuits.
TXSLEW0 pin
floating
floating
floating
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high
high
high
low
low
low
TXSLEW1 mode
floating
floating
floating
high
high
high
low
low
low
+/-1% series resistor. The resistor is
Rise/Fall time
0.5 ns
1.0 ns
1.5 ns
2.0 ns
2.5 ns
3.0 ns
3.5 ns
4.0 ns
4.5 ns
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