CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet - Page 23

• Manufacturer Part Number: CS8952T-CQ
• Description: 100BASE E-X AND 10BASE-T TRANSCEIVER
• Manufacturer: Cirrus Logic

Auto-Negotiation Configuration
At power-up and reset times, the auto-negotiation
mode is selected via the auto-negotiation input pins
(AN[1:0]). These three-level input pins are sam-
pled during power-up or reset. If either of these
pins is left unconnected, internal logic pulls its sig-
nal to a mid-range value, designated as 'M' in the
following table. Either pin may also be connected
to a 5 to 25 MHz TTL-level clock source, designat-
ed as ‘C’ in the following table. A minimum of 8
rising edges of the clock are required while RESET
is asserted for the AN[1:0] input logic to interpret
the input as ‘C’.
Auto-Negotiation may also be enabled and the ad-
vertised capabilities modified under software con-
trol through bit 8 of the Basic Mode Control
Register (address 00h), and bits 5, 6, 7, 8, and 10 of
DS206TPP2
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
AN1 pin
M
M
M
M
C
C
C
C
0
1
0
0
1
1
1
0
1. The Auto-Negotiation Advertisement Register will be modified to advertise 100 Mb/s
2. The Auto-Negotiation Advertisement Register will be modified to advertise
3. The Auto-Negotiation Advertisement Register will be modified to advertise
Full/Half.
100/10 Mb/s Full.
100/10 Mb/s Half.
AN0 pin
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
M
M
M
M
C
C
C
C
0
1
0
1
0
1
1
0
Table 5. Auto-negotiation Mode Selection
Forced/Auto
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Forced
Forced
Forced
Forced
Forced
Forced
Forced
the Auto-Negotiation Advertisement Register (ad-
dress 04h).
Auto-Negotiation Operation
Auto-Negotiation encapsulates information within
a burst of closely spaced Link Integrity Test Pulses,
referred to as a Fast Link Pulse (FLP) Burst. The
FLP Burst consists of a series of Link Integrity
Pulses which form an alternating clock / data se-
quence. Extraction of the data bits from the FLP
Burst yields a Link Code Word which identifies the
capability of the remote device.
In order to support legacy 10 and 100 Mb/s devic-
es, the CS8952T also supports parallel detection. In
parallel detection, the CS8952T monitors activity
on the media to determine the capability of the link
partner even without auto-negotiation having oc-
curred.
100/10 Mb/s
100/10 Mb/s
100/10 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
10 Mb/s
10 Mb/s
10 Mb/s
10 Mb/s
10 Mb/s
Speed
Full/Half Duplex
Half (Note 3)
Full (Note 1)
Full (Note 2)
Full/Half
Full/Half
Full/Half
Half
Half
Half
Half
Half
Full
Full
Full
Full
Full
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