CS8952T-CQ Cirrus Logic, CS8952T-CQ Datasheet - Page 57

• Manufacturer Part Number: CS8952T-CQ
• Description: 100BASE E-X AND 10BASE-T TRANSCEIVER
• Manufacturer: Cirrus Logic

Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)
DS206TPP2
3
2
1
0
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
BIT
Premature End
Error Report Select
Link Error Report
Enable
Packet Error Report
Enable
Code Error Report
Enable
NAME
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 0
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
TYPE
RESET
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
When set, this bit causes link errors to be reported by
a value of 3h on RXD[3:0] and the assertion of
RX_ER. When clear, link errors are not reported
across the MII.
When set, this bit causes packet errors to be reported
by a value of 2h on RXD[3:0] and the assertion of
RX_ER. When clear, packet errors are not reported
across the MII.
When set, code errors are reported and transmitted
on RXD[3:0].
When clear, this bit enables the Code Error Report
values on RXD[3:0] as selected by the Code Error
Report Select bit and also causes the assertion of
TX_ER to transmit a HALT code group.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DESCRIPTION
57