AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 24

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the
channel dividers does not exceed its specified maximum frequency
(1.6 GHz, see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (0x18<0>) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 23 should be used.
REFIN (REF1)
REFIN (REF2)
BYPASS
RESET
SYNC
SCLK
SDIO
SDO
CLK
CLK
PD
CS
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
AD9518-2
CONTROL
DIGITAL
SWITCHOVER
SERIAL
STATUS
LOGIC
REFERENCE
PORT
REF_ SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
VCO STATUS
N DIVIDER
DIVIDER
Figure 28. Internal VCO and Clock Distribution
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. 0 | Page 24 of 64
DIVIDE BY
DIVIDE BY
DIVIDE BY
1 TO 32
1 TO 32
1 TO 32
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
Table 23. Settings When Using Internal VCO
Register
0x10<1:0> = 00b
0x10 to 0x1E
0x18<0> = 0,
0x232<0> = 1
0x18<0> = 1,
0x232<0> = 1
0x1E0<2:0>
0x1E1<0> = 0b
0x1E1<1> = 1b
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
Function
PLL normal operation (PLL on)
PLL settings; select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration
Reset VCO calibration (first time after
power-up, this does not have to be done
but must be done subsequently)
Initiate VCO calibration
VCO divider set to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, or divide-by-6
Use the VCO divider as source for
distribution section
VCO selected as the source
CPRSET VCP
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
LD
CP
STATUS
CP