AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 54

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
1C
1C
1C
1C
1C
1C
1C
1C
1D
AD9518-2
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<4>
Disable
Switchover
Deglitch
Select REF2 If 0x1C<5> = 0, selects reference for PLL.
Use REF_SEL If 0x1C<4> = 0 (manual), set method of PLL reference selection.
Pin
Automatic
Reference
Switchover
Stay on REF2 Stays on REF2 after switchover.
REF2
Power On
REF1
Power On
Differential
Reference
PLL Status
Register
Disable
Description
<4> <3> <2> <1>
1
1
1
1
1
1
1
1
1
1
1
1
1
Disables or enables the switchover deglitch circuit.
<7> = 0; enables switchover deglitch circuit.
<7> = 1; disables switchover deglitch circuit.
<6> = 0; selects REF1.
<6> = 1; selects REF2.
<5> = 0; use 0x1C<6>.
<5> = 1; use REF_SEL pin.
Automatic or manual reference switchover. Single-ended reference mode must be selected by 0x1C<0> = 0.
<4> = 0; manual reference switchover.
<4> = 1; automatic reference switchover.
<3> = 0; return to REF1 automatically when REF1 status is good again.
<3> = 1; stay on REF2 after switchover. Do not automatically return to REF1.
When automatic reference switchover is disabled, this bit turns the REF2 power on.
<2> = 0; REF2 power off.
<2> = 1; REF2 power on.
When automatic reference switchover is disabled, this bit turns the REF1 power on.
<1> = 0; REF1 power off.
<1> = 1; REF1 power on.
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the
automatic switchover for REF1 and REF2 to work.
<0> = 0; single-ended reference mode.
<0> = 1; differential reference mode.
Disables the PLL status register readback.
<4> = 0; PLL status register enable.
<4> = 1; PLL status register disable.
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
<0>
1
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Rev. 0 | Page 54 of 64
Signal at REFMON Pin
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential mode);
active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (status of VCO).
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active (active low).
LD pin comparator output (active low).