AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 39

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

IINPUT TO CHANNEL DIVIDER
A SYNC operation brings all outputs that have not been
excluded (by the nosync bit) to a preset condition before
allowing the outputs to begin clocking in synchronicity. The
preset condition takes into account the settings in each of the
channel’s start high bit and its phase offset. These settings
govern both the static state of each output when the SYNC
operation is happening and the state and relative phase of the
outputs when they begin clocking again upon completion of the
SYNC operation. Between outputs and after synchronization,
this allows for the setting of phase offsets.
The AD9518 outputs are in pairs, sharing a channel divider
per pair. The synchronization conditions apply to both outputs
of a pair.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
LVPECL Clock Outputs: OUT0 to OUT5
The LVPECL differential voltage (V
~400 mV to ~960 mV, see 0xF0:0xF5<3:2>. The LVPECL
outputs have dedicated pins for power supply (VS_LVPECL),
allowing for a separate power supply to be used. V
from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
SYNC PIN
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
INPUT TO CLK
OUTPUT OF
OD
) is selectable from
Figure 40. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
S_LVPECL
2
3
can be
CHANNEL DIVIDER OUTPUT STATIC
4
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5
6
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
RESET MODES
The AD9518 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When V
Applied
A power-on reset (POR) is issued when the V
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 41. At
power-on, the AD9518 also executes a SYNC operation, which
brings the outputs into phase alignment according to the default
settings.
7
8
Figure 41. LVPECL Output Simplified Equivalent Circuit
9
10
11
GND
12
13
3.3V
14
1
OUT
OUT
OUTPUT CLOCKING
CHANNEL DIVIDER
S
power supply is
AD9518-2
S
Is