AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 28

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs,
and tells the CP to pump up or pump down to charge or
discharge the integrating node (part of the loop filter). The
integrated and filtered CP current is transformed into a voltage
that drives the tuning node of the internal VCO through the LF
pin (or the tuning pin of an external VCO) to move the VCO
frequency up or down. The CP can be set (0x10<6:4>) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), for pump up, or for pump
down (test modes). The CP current is programmable in eight
steps from (nominally) 600 μA to 4.8 mA. The exact value of
the CP current LSB is set by the CP_RSET resistor, which is
nominally 5.1 kΩ.
On-Chip VCO
The AD9518 includes an on-chip VCO covering the frequency
range shown in Table 2. Achieving low VCO phase noise was a
priority in the design of the VCO.
To tune over the wide range of frequencies covered by this
VCO, ranges are used. This is largely transparent to the user but
is the reason that the VCO must be calibrated when the PLL
loop is first set up. The calibration procedure ensures that the
VCO is operating within the correct band range for the frequency
that it is asked to produce. See the VCO Calibration section for
additional information.
The on-chip VCO is powered by an on-chip, low dropout
(LDO), linear voltage regulator. The LDO provides some
isolation of the VCO from variations in the power supply
voltage level. The BYPASS pin should be connected to ground
by a 220 nF capacitor to ensure stability. This LDO employs the
same technology used in the anyCAP® line of regulators from
Analog Devices, Inc., making it insensitive to the type of
capacitor used. Driving an external load from the BYPASS pin
is not supported.
PLL External Loop Filter
When using the internal VCO, the external loop filter should be
referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for the PLL
is shown in Figure 31. A loop filter must be calculated for each
desired PLL configuration. The values of the components
depend upon the VCO frequency, the K
the CP current, the desired loop bandwidth, and the desired
phase margin. The loop filter affects the phase noise, the loop
settling time, and the loop stability. A knowledge of PLL theory
is necessary for understanding the subject of loop filter design.
There are tools available, such as ADIsimCLK, that can help
with the calculation of a loop filter according to the application
requirements.
VCO
, the PFD frequency,
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PLL Reference Inputs
The AD9518 features a flexible PLL reference input circuit that
allows either a fully differential input or two separate single-
ended inputs. The input frequency range for the reference
inputs is specified in Table 2. Both the differential and the
single-ended inputs are self-biased, allowing for easy ac
coupling of input signals.
The differential input and the single-ended inputs share the two
pins, REFIN (REF1)/ REFIN (REF2). The desired reference input
type is selected and controlled by 0x1C (see Table 41 and Table 43).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Table 2) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing required of the
driver and overcomes the offset.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down, and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side ( REFIN ) should be
decoupled via a suitable capacitor to a quiet ground. Figure 32
shows the equivalent circuit of REFIN.
Figure 31. Example of External Loop Filter for PLL
AD9518-2
CHARGE
PUMP
VCO
LF
CP
BYPASS
C
BP
= 220nF
C1
R1
C2
R2
C3