AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 4

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
SPECIFICATIONS
Typical (typ) is given for V
unless otherwise noted. Minimum (min) and maximum (max) values are given over full V
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
V
V
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
REFERENCE INPUTS
S
S_LVPECL
CP
Frequency Range
VCO Gain (K
Tuning Voltage (V
Frequency Pushing (Open-Loop)
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
Differential Mode (REFIN, REFIN)
Dual Single-Ended Mode (REF1, REF2)
Input Capacitance
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
VCO
)
T
)
Min
3.135
2.375
V
S
S
= V
S_LVPECL
Typ
3.3
4.12
5.1
220
= 3.3 V ± 5%; V
Max
3.465
V
5.25
S
Min
2050
0.5
0
1.35
1.30
4.0
4.4
20
0
2.0
−100
Unit
V
V
V
kΩ
kΩ
nF
Typ
50
1
−107
−124
250
1.60
1.50
4.8
5.3
0.8
2
S
≤ V
This is 3.3 V ± 5%
This is nominally 2.5 V to 3.3 V ± 5%
This is nominally 3.3 V to 5.0 V ± 5%
Test Conditions/Comments
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
CP
Rev. 0 | Page 4 of 64
≤ 5.25 V; T
Max
2335
V
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
CP
− 0.5
A
= 25°C; R
Unit
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
μA
pF
SET
f = 2175 MHz
f = 2175 MHz
Self-bias voltage of REFIN
Test Conditions/Comments
See Figure 11
See Figure 6
V
this range, the CP spurs may increase due to CP
up/down mismatch
Differential mode (can accommodate single-
ended input by ac grounding undriven input)
Frequencies below about 1 MHz should be
dc-coupled; be careful to match V
PLL figure of merit increases with increasing
slew rate; see Figure 10
Self-bias voltage of REFIN
Self-biased
Self-biased
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed V
Each pin, REFIN/REFIN (REF1/REF2)
S
CP
= 4.12 kΩ; CP
and T
≤ V
S
A
when using internal VCO; outside of
(−40°C to +85°C) variation.
1
1
RSET
= 5.1 kΩ,
S
p-p
1
1
CM
(self-bias voltage)