AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 34

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9518-2
VCO Calibration
The AD9518 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be
present. During the first initialization after a power-up or a
reset of the AD9518, a VCO calibration sequence is initiated by
setting 0x18<0> = 1b. This can be done as part of the initial
setup before executing update registers (0x232<0> = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting 0x18<0> = 0b, executing an update registers
operation, setting 0x18<0> = 1b, and executing another update
registers operation. A readback bit (0x1F<6>) indicates when a
VCO calibration is finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is:
• Program the PLL registers to the proper values for the PLL loop.
• For the initial setting of the registers after a power-up or
• A SYNC operation is initiated internally, causing the outputs
• VCO calibrates to the desired setting for the requested VCO
• Internally, the SYNC signal is released, allowing outputs to
• PLL loop is closed.
• PLL locks.
reset, initiate VCO calibration by setting 0x18<0> = 1b.
Subsequently, whenever a calibration is desired, set 0x18<0> =
0b, update registers, and set 0x18<0> = 1b, update registers.
to go to a static state determined by normal SYNC function
operation.
frequency.
continue clocking.
REFIN (REF1)
REFIN (REF2)
BYPASS
CLK
CLK
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
N DIVIDER
DIVIDER
Figure 37. Reference and VCO Status Monitors
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. 0 | Page 34 of 64
0
1
VCO STATUS
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
A SYNC is executed during the VCO calibration; therefore, the
outputs of the AD9518 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 43
(0x18<2:1>).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
where:
f
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(0x18<2:1>).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Table 28. Example Time to Complete a VCO Calibration
with Different f
f
100
10
10
REFIN
REFIN
f
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
is the frequency of the REFIN signal.
(MHz)
CAL_CLOCK
= f
R Divider
1
10
100
FREQUENCY
DETECTOR
REFIN
REFIN
DETECT
PHASE
LOCK
/(R × cal_div)
Frequencies
PFD
100 MHz
1 MHz
100 kHz
CPRSET VCP
CHARGE
PUMP
HOLD
Time to Calibrate VCO
88 μs
8.8 ms
88 ms
LD
CP
STATUS