AD9518-2 Analog Devices, Inc., AD9518-2 Datasheet - Page 58

• Manufacturer Part Number: AD9518-2
• Description: 6-output Clock Generator With Integrated 2.2 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
192
192
193
193
194
194
194
194
194
195
195
AD9518-2
Table 45. LVPECL Channel Dividers
<7:4> Divider 0 Low Cycles
<3:0> Divider 0 High Cycles
<7>
<6>
<5>
<4>
<3:0> Divider 0 Phase Offset
<1>
<0>
<7:4> Divider 1 Low Cycles
<3:0> Divider 1 High Cycles
<7>
<6>
<5>
<4>
<3:0> Divider 1 Phase Offset
<1>
<0>
Divider 0 Bypass
Divider 0 Nosync
Divider 0 Force High
Divider 0 Start High
Divider 0 Direct to Output
Divider 0 DCCOFF
Divider 1 Bypass
Divider 1 Nosync
Divider 1 Force High
Divider 1 Start High
Divider 1 Direct to Output
Divider 1 DCCOFF
Description
Number of clock cycles of the divider input during which divider output stays low.
Number of clock cycles of the divider input during which divider output stays high.
Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
<1> = 0; OUT0 and OUT1 are connected to Divider 0.
<1> = 1;
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT0 and OUT1.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT0 and OUT1.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
Number of clock cycles of the divider input during which divider output stays low.
Number of clock cycles of the divider input during which divider output stays high.
Bypasses and powers down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
<1> = 0; OUT2 and OUT3 are connected to Divider 1.
<1> = 1;
If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT2 and OUT3.
If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT2 and OUT3.
If 0x1E1<1:0> = 01b, there is no effect.
Duty-cycle correction function.
<0> = 0; enable duty-cycle correction.
<0> = 1; disable duty-cycle correction.
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