cy2sstu32866 SpectraLinear Inc, cy2sstu32866 Datasheet

cy2sstu32866

Manufacturer Part Number

cy2sstu32866

Description

1.8v, 25-bit 1 1 Or 14-bit 1 2 Jedec-compliant Data Register With Parity

Manufacturer

SpectraLinear Inc

Datasheet

1.CY2SSTU32866.pdf (24 pages)

Current page: 1 of 24
Download datasheet (230Kb)

Rev 1.0, November 25, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Features

Functional Description

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized to

drive the DDR-II DIMM load. The CY2SSTU32866 operates

from a differential clock (CK and CK#). Data are registered at

the crossing of CK going high, and CK# going LOW.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when LOW) to B configuration (when

HIGH). The C1 input controls the pinout configuration from

25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).

The device monitors both DCS# and CSR# inputs and will gate

the Qn outputs from changing states when both DCS# and

• Operating frequency: DC to 500 MHz

• Supports DDRII SDRAM

• Two operations modes: 25 bit (1:1) and 14 bit (1:2)

• 1.8V operation

• Fully JEDEC-compliant (JESD 82-10)

• 96-ball FBGA

1:1 Register C0 = 0, C1=0

DCKE PPO

DODT QERR# GND

PAR_IN RST#

CK#

D10

D11

D12

D13

D14

D15

D16

D17

D18

DCS#

CSR#

D19

D20

D21

D22

D23

D24

D25

VREF

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

VREF

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant

QCKE NC

QODT NC

QCS#

ZOH

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q18

ZOL

Q19

Q20

Q21

Q22

Q23

Q24

Q25

Pin Configuration

Tel:(408) 855-0555

DCKE PPO

DODT QERR# GND

PAR_IN RST#

CK#

D10

D11

D12

D13

D14

1:2 Register A C0 = 0, C1=1

DCS#

CSR#

VREF

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

VREF

CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,

the Qn outputs will function normally. The RESET# input has

priority over the DCS# and CSR# control and will force the

outputs LOW. If the DCS#-control functionality is not desired,

the CSR# input can be hardwired to ground, in which case the

set-up time requirement for DCS# would be the same as for

the other D data inputs.

The device supports low-power standby operation. When the

reset input (RESET#) is LOW, the differential input receivers

are disabled, and undriven (floating) data, clock, and reference

voltage (VREF) inputs are allowed. In addition, when RESET#

is LOW, all registers are reset and all outputs are forced LOW.

The LVCMOS RESET# and Cn inputs must always be held at

a valid logic HIGH or LOW level. To ensure defined outputs

from the register before a stable clock has been supplied,

RESET# must be held in the LOW state during power-up.

In the DDR-II RDIMM application, RESET# is specified to be

completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven low quickly, relative to the time to

disable the differential input receivers. However, when coming

out of reset, the register will become active quickly, relative to

the time to enable the differential input receivers.

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

Fax:(408) 855-0550

QCKEA QCKEB

Q2A

Q3A

QODTA QODTB

Q5A

Q6A

QCSA# QCSB#

ZOH

Q8A

Q9A

Q10A

Q11A

Q12A

Q13A

Q14A

Data Register with Parity

Q2B

Q3B

Q5B

Q6B

ZOL

Q8B

Q9B

Q10B

Q11B

Q12B

Q13B

Q14B

CY2SSTU32866

PAR_IN RST#

CK#

D10

DODT NC

D12

D13

DCKE NC

1:2 Register B C0 = 1, C1=1

www.SpectraLinear.com

PPO

QERR# GND

DCS#

CSR#

VREF

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

VREF

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

Page 1 of 24

Q1A

Q2A

Q3A

Q4A

Q5A

Q6A

QCSA# QCSB#

ZOH

Q8A

Q9A

Q10A

QODTA QODTB

Q12A

Q13A

QCKEA QCKEB

Q1B

Q2B

Q3B

Q4B

Q5B

Q6B

ZOL

Q8B

Q9B

Q10B

Q12B

Q13B

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