cy28rs680-2 SpectraLinear Inc, cy28rs680-2 Datasheet
cy28rs680-2
Related parts for cy28rs680-2
cy28rs680-2 Summary of contents
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... VDD_SRC_IO SRCC2 19 SRCT[0:7] VSS_SRC 20 SRCC[0:7] VDD_SRC 21 SRCT1 22 SRCC1 23 VDD_SRC 24 VSS_SRC 25 VDD48 ATIGC3 26 48M[0:1] ATIGT3 27 CLKREQB TSSOP/SSOP Tel:(408) 855-0555 Fax:(408) 855-0550 CY28RS680-2 ATIG REF USB_48 REF0 55 REF1 54 REF2 53 VDD_HTT 52 HTT66 51 VSS_HTT 50 CLKREQA# 49 AMD_CPUT0 48 AMD_CPUC0 47 VSS_CPU 46 AMD_CPUT1 ...
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... Ground for CPU outputs 50 CLKREQ#A I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard specification. PU This pin has an internal pull-up selected SRC output is enabled selected SRC output is disabled. Rev 1.0, November 22, 2006 ADVANCE INFORMATION Description ® Type-3A buffer. CY28RS680-2 Page ...
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... Byte Count from slave – 8 bits 38 Acknowledge 46:39 Data byte 1 from slave – 8 bits 47 Acknowledge 55:48 Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge CY28RS680-2 Block Read Protocol Description Page ...
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... SRC[T/C]0 Output Enable 0 = Disable (Hi-Z Enable Reserved Reserved ATIG[T/C]3 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]2 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]1 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]0 Output Enable 0 = Disable (Hi-Z Enable Reserved CPU[T/C]1 Output Enable 0 = Disable (Hi-Z Enable CY28RS680-2 Byte Read Protocol Description Description Description Page ...
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... ATIG_PLL (PLL2) Spread Spectrum Enable 0 = Spread Off Spread On SRC_PLL (PLL3) Spread Spectrum Enable 0 = Spread Off Spread On USB48 Output Drive Strength Reserved REF Output Drive Strength CY28RS680-2 Description Description ATIG Output N 111.33–167 MHz 167–250 100–125 MHz 200–250 166– ...
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... Vendor ID Bit 0 N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] N counter Control bit [7:0] CLKREQC# Controls ATIG3 0 = Not controlled Controlled CY28RS680-2 Description Description Description Description Description Page ...
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... Reserved (test mode) 001 Time_Scale 010 Time_Scale 011 Time_Scale 100 Time_Scale 101 Time_Scale 110 Time_Scale 111 Time_Scale Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable Enable CY28RS680-2 Description Description Description Page ...
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... Used when RESET_IN# is asserted or the Watch Dog timer times out. This will be the safe value or last known good frequency of the CPU set by the user before engaging in any overclocking exercise. M values revert to those set by the FS[C:A] pins ATIG DAF bit N8 CY28RS680-2 Description Description Description Description ...
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... Crystal Recommendations The CY28RS680-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS680-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... The safe frequency register is accessible via SMBUS (Bytes 18 & 19). The clock outputs must be stable at the correct safe frequency at least 2 ms before the deassertion of RESET_IN#. CY28RS680-2 Page ...
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... The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0. average over 1-μs duration Over 150 ms CY28RS680-2 Min. Max. –0.5 4.6 –0.5 4.6 –0 ...
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... F Math averages Figure 7 Math averages Figure 7 See Figure 7. Measure SE Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28RS680-2 Min. Max. Unit 2 7 V/ns 0.4 2.3 V –300 300 ppm – ...
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... Measured at 20% and 60% Measured at 1.5V Measured at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V@1 μs Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V@10 μs CY28RS680-2 Min. Max. Unit 175 700 ps – – 125 ps – 125 ps 660 850 mv –150 – ...
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... L ” ” ” ” ” ” ” CY28RS680 Page ...
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... Figure 7. 0.7V Load Configuration 125 ohms 3900pF 169 ohms 3900pF Figure 8. CPU Output Load Configuration Package Type CY28RS680 ...
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... MAX. 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE CY28RS680-2 DIMENSIONS IN INCHES MIN. MAX. 0.005 .010 0.010 0.024 0.040 0°-8° PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. GAUGE PLANE ...