cy28349oxct SpectraLinear Inc, cy28349oxct Datasheet
cy28349oxct
Related parts for cy28349oxct
cy28349oxct Summary of contents
Page 1
FTG for Intel Features ® • Compatible to Intel CK-Titan & CK-408 Clock Synthe- sizer/Driver Specifications • System frequency synthesizer for Intel Brookdale 845 ® and Brookdale - G Pentium 4 Chipsets • Programmable clock output frequency with less than ...
Page 2
Pin Definitions Pin Name Pin No REF0/MULTSEL0 48 REF1/MULTSEL1 1 CPU0:1, CPU0:1# 41, 38, 40, 37 CPU_ITP, 44, 45 CPU_ITP# 3V66_0:2 31, 30, 28 PCI_F0/FS2 6 PCI_F1/FS3 7 PCI_F2 8 PCI0/FS4 10 PCI1:6 11, 12, 14, ...
Page 3
Pin Definitions (continued) Pin Name Pin No. PWR_DWN# 42 SCLK 26 SDATA 25 RST# 20 (open- IREF 35 VTT_PWRGD# 19 VDD_REF 18, 24, VDD _PCI, 32, 39, 46 VDD_48MHz, VDD_3V66, VDD_CPU GND_PCI, 5, 13, 21, 29, GND_48MHz, 36, ...
Page 4
Swing Select Functions Board Target MULTSEL1 MULTSEL0 Trace/Term ...
Page 5
Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. ...
Page 6
Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 2:8 Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of ...
Page 7
Data Byte 1 (continued) Bit Pin# Name Bit 2 28 3V66_2 Bit 1 30 3V66_1 Bit 0 31 3V66_0 Data Byte 2 Bit Pin# Name Bit 7 -- Reserved Bit 6 17 PCI6 Bit 5 16 PCI5 Bit 4 15 ...
Page 8
Data Byte 5 Bit Pin# Name Bit 7 10 Latched FS4 input Bit 6 7 Latched FS3 input Bit 5 6 Latched FS2 input Bit 4 23 Latched FS1 input Bit 3 22 Latched FS0 input Bit 2 -- FS_Override ...
Page 9
Data Byte 8 (continued) Bit Pin# Name Bit 5 -- WD_TIMER4 Bit 4 -- WD_TIMER3 Bit 3 -- WD_TIMER2 Bit 2 -- WD_TIMER1 Bit 1 -- WD_TIMER0 Bit 0 -- WD_PRE_SCALER Data Byte 9 Bit Pin# Name Bit 7 -- ...
Page 10
Data Byte 10 Bit Pin# Name Bit 7 -- CPU_Skew2 Bit 6 -- CPU_Skew1 Bit 5 -- CPU_Skew0 Bit 4 -- Fixed 3V66/PCI Bit 3 -- PCI_Skew1 Bit 2 -- PCI_Skew0 Bit 1 -- 3V66_Skew1 Bit 0 -- 3V66_Skew0 Data ...
Page 11
Data Byte 12 (continued) Bit Pin# Name Bit 6 -- ROCV_FREQ_M6 Bit 5 -- ROCV_FREQ_M5 Bit 4 -- ROCV_FREQ_M4 Bit 3 -- ROCV_FREQ_M3 Bit 2 -- ROCV_FREQ_M2 Bit 1 -- ROCV_FREQ_M1 Bit 0 -- ROCV_FREQ_M0 Data Byte 13 Bit Pin# ...
Page 12
Data Byte 16 Bit Pin# Name Bit 7 -- Reserved Bit 6 -- Reserved Bit 5 -- Reserved Bit 4 -- Reserved Bit 3 -- Reserved Bit 2 -- Reserved Bit 1 -- Reserved Bit 0 -- Reserved Data Byte ...
Page 13
Table 4. Frequency Selection Table Input Conditions FS4 FS3 FS2 FS1 SEL4 SEL3 SEL2 SEL1 ...
Page 14
Table 5. Register Summary (continued) Name CPU_FSEL_N, When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either ...
Page 15
Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage.............................................. –0. [2] Operating Conditions Over which Electrical Parameters are Guaranteed Parameter ...
Page 16
Switching Characteristics Over the Operating Range Parameter Output t All Output Duty Cycle 1 t CPU Rise Time 2 t 48MHz, REF Rising Edge Rate 2 t PCI, 3V66, Rising Edge Rate 2 t CPU Fall Time 3 ...
Page 17
Switching Waveforms Duty Cycle Timing (Single Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock ...
Page 18
Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Rev 1.0, November 24, 2006 CY28349 Page ...
Page 19
Layout Example +3.3V Supply FB 0.005μ VDDQ3 5Ω Dale ILB1206 - 300 (300Ω @ 100 MHz) Cermaic Caps C3 = 10–22 μ VIA to GND plane layer Note: Each ...
Page 20
... Lead-free CY28349OXC 48-pin Small Shrunk Outline Package (SSOP) CY28349OXCT 48-pin Small Shrunk Outline Package (SSOP) - Tape and Reel Package Diagram While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use ...