cy28352oi-400t SpectraLinear Inc, cy28352oi-400t Datasheet

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cy28352oi-400t

Manufacturer Part Number
cy28352oi-400t
Description
Differential Clock Buffer/driver Ddr400 And Ddr333-compliant
Manufacturer
SpectraLinear Inc
Datasheet
Differential Clock Buffer/Driver DDR400 and DDR333-Compliant
Rev 1.0, November 28, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Features
• Supports 333-MHz and 400-MHz DDR SDRAM
• 60–273-MHz operating frequency
• Phase-locked loop (PLL) clock distribution for double
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize
• Conforms to DDRI specification
• Spread Aware™ for electromagnetic interference (EMI)
• 28-pin SSOP package
Block Diagram
data rate synchronous DRAM applications
output to clock input
reduction
SDATA
CLKIN
SCLK
AVDD
FBIN
PLL
Interface
Serial
Logic
10
FBOUT
Tel:(408) 855-0555
CLKT5
CLKT0
CLKC0
CLKT1
CLKC1
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKC5
CLKT2
Description
This PLL clock buffer is designed for 2.6V
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low-jitter output differential clocks.
Pin Configuration
CLKC0
CLKC1
CLKC2
CLKT0
CLKT1
CLKT2
CLKIN
AGND
AVDD
SCLK
GND
VDD
VDD
Fax:(408) 855-0550
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 pin SSOP
CY28352-400
28
27
26
25
24
23
22
21
20
19
18
17
16
15
www.SpectraLinear.com
CLKC3
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
GND
DD
Page 1 of 7
and 2.6AV
DD
DD
is

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cy28352oi-400t Summary of contents

Page 1

Differential Clock Buffer/Driver DDR400 and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60–273-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs ...

Page 2

Pin Description Pin Number Pin Name I/O 8 CLKIN I Complementary Clock Input. 20 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. Input 2,4,13,17,24, Clock Outputs CLKT(0: 1,5,14,16,25, Clock Outputs CLKC(0: ...

Page 3

Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: • Command Code byte • Byte Count byte. Byte0: Output Register1 (1 = Enable Disable) Bit @Pup ...

Page 4

Absolute Maximum Conditions Input Voltage Relative to V :...............................V SS Input Voltage Relative ............... Storage Temperature: ................................ –65° 150°C Operating Temperature:................................ –40°C to +85°C Maximum Power Supply: ................................................ 3.5V [4] ...

Page 5

AC Electrical Specifications (continued) Parameter Description tCCJ Cycle-to-Cycle Jitter [12] tjit(h-per) Half-period jitter LOW-to-HIGH Propagation Delay, tPLH CLKIN to CLKT[0:5] HIGH-to-LOW Propagation Delay, tPHL CLKIN to CLKT[0:5] tSKEW Any Output to Any Output Skew [11] tPHASE Phase Error tPHASEJ Phase ...

Page 6

CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0: T[0 :5 [0:5] CLKIN 50 Ω FBIN 50 Ω Figure 7. Differential Signal Using Direct Termination Resistor Rev 1.0, ...

Page 7

... Part Number CY28352OC–400 CY28352OC–400T CY28352OI–400 CY28352OI–400T Package Drawing and Dimensions 28-lead (5.3 mm) Shrunk Small Outline Package O28 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use ...

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