cy28508 SpectraLinear Inc, cy28508 Datasheet
cy28508
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cy28508 Summary of contents
Page 1
... SSOP package Pin Configuration REF 2.5V CPUT0 PLL CPUC0 CPUT1 OD CPUC1 CPUT2 CPUC2 CPU_STOP# Tel:(408) 855-0555 Fax:(408) 855-0550 CY28508 2 C addresses 2 C operation 28 VDDQ REF 1 27 CPUT0 VDDX 2 26 CPUC0 XIN 3 25 ...
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... Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corre- sponding byte write and byte read protocol. The Byte Count value returned is 09h. The slave receiver address is either D2 or D4, depending on the state of the ADDRSEL pin. CY28508 Description Page ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop CY28508 Page ...
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... Select spread percentage 1. See Table 4 Select spread percentage 0. See Table 4 REF Output Enable 0 = Disabled (three-stated)), 1 = Enabled CPU2 Output Enable 0 = Disabled (three-stated Enabled CPU1 Output Enable 0 = Disabled (three-stated Enabled CPU0 Output Enable 0 = Disabled (three-stated Enabled Description Description CY28508 Page ...
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... Reserved, set = Reserved, set = Reserved, set = 0. Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508 Bit @Pup 7 1 FSEL Control FSEL FSEL FSEL MN0 select MN1 select. Only valid when B6b7 = 0. ...
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... Byte 7: Dial-a-Frequency Control Register N3 - Only bit 7 is used by the CY28508 Bit @Pup Setting the total step time index during Smooth-Track for each increment or decrement during Smooth-Track. The default 2048 and if you program 1024, the step time will be half of this value. ...
Page 7
... Crystal Recommendations The CY28508 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28508 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... When CPU_STOP# pin is asserted, all CPUT/C outputs will be stopped after being sampled by two rising edges of the CPUT clocks. The final state of the stopped CPU signals is CPUT = LOW and CPU0C = HIGH. < Figure 4. Power-up Signal Timing CY28508 ( ...
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... The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles. CPU_STOP# CPUT CPUC CPUT (internal) CPUC Rev 1.0, November 24, 2006 Figure 5. CPU_STOP# Assertion Waveform Figure 6. CPU_STOP# Deassertion Waveform CY28508 Page ...
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... See Figure 7 . For all pins including XIN Both rising and falling Output is 224.7 MHz with VCO running 666.6 MHz Output is 224.7 MHz with VCO running 666.6 MHz Output is 224.7 MHz with VCO running 666.6 MHz CY28508 Min. Max. Unit –0.5 5.5 V –0.5 5.5 V – ...
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... Outputs will be as shown in Figure 6 Worst-Corner Max Slew ICP Rate (kHz/μS) B2b7 100 x1 140 Worst-Corner Max Slew ICP Rate (kHz/μS) B2b7 150 x1 200 x1 100 x1 CY28508 Min. Typ. Max. Unit 180 225 mA 124 155 Min. ...
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... CPUT 33Ω CPUC VDDQ 2. Rev 1.0, November 24, 2006 (50Ω) T Measurement Point PCB 50Ω 5pF 8 inches (50Ω) T Measurement Point PCB 50Ω 5pF 8 inches Figure 7. Output Test Loading Figure 8. CPU Signaling CY28508 Page ...
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... Rev 1.0, November 24, 2006 Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel CY28508 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Page ...