cy28508 SpectraLinear Inc, cy28508 Datasheet - Page 4

• Manufacturer Part Number: cy28508
• Description: 333 Mhz Low-voltage Differential Sscg
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 24, 2006
Serial Control Registers
Byte 0 : CPU Control Register
Table 4. Spread Spectrum Table
Glitch-free operation for both enabling and disabling Spread
Spectrum. To achieve down spread operation, reprogram the
N register to drop the frequency by half the spread amount.
Byte 1: Dial-a-Frequency Control Register N0 [default = 112.35 MHz, N = 43d, ODSEL = 1]
Byte 2: Dial-a-Frequency Control Register M0 [default = 112.35MHz, M = 49d, ODSEL = 1]
SST1 SST0
0
0
1
1
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
1
@Pup
@Pup
@Pup
Pin 6
±0.125% Center spread Lexmark™ profile
±0.25% Center spread Lexmark profile
±0.5% Center spread Lexmark profile
±0.5% Center spread Linear profile
HW
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
0
1
0
1
0
1
1
Test Mode: 0 = normal operation, 1 = phase-locked loop (PLL) bypass mode, when OD = 3 then /3, when
OD = 2 then /2.
N6, most significant bit (MSB).
N5
N4
N3
N2
N1
N0, least significant bit (LSB).
The charge pump current value during Smooth-Track can be programmed to normal mode (2xICP) by
setting this bit to “1.” The default value of “0” (1xICP) will program the charge pump current to half of normal
and will reduce the bandwidth and hence the slew rate.
FSEL operational status, whether HW or SW. 0 = M&N0, 1 = M&N1 (read only).
M5 MSB
M4
M3
M2
M1
M0, LSB
SS_ENABLE
CPUT/C2
CPUT/C1
CPUT/C0
Name
LOCK
SST1
SST0
REF
% Spread
Lock Detect: 0 = not at final frequency, 1 = VCO locked (read-only).
0 = disabled, 1 = enabled.
Select spread percentage 1. See Table 4
Select spread percentage 0. See Table 4
REF Output Enable
0 = Disabled (three-stated)), 1 = Enabled
CPU2 Output Enable
0 = Disabled (three-stated), 1 = Enabled
CPU1 Output Enable
0 = Disabled (three-stated), 1 = Enabled
CPU0 Output Enable
0 = Disabled (three-stated), 1 = Enabled
Description
Description
Description
CY28508
Page 4 of 13