cy28549 SpectraLinear Inc, cy28549 Datasheet
cy28549
Related parts for cy28549
cy28549 Summary of contents
Page 1
... VDD_SRC 2 53 SRCC_2 3 52 SRCT_2 4 51 SRCC_1/SATAC 5 50 SRCT_1/SATAT 6 49 VDD_SRC 7 48 SRCC_0 / LCD100MC 8 47 SRCT_0 / LCD100MT CY28549 9 46 CLKREQ1 FSB/TEST_MODE 11 44 DOT96C / 27M_SS 12 43 DOT96T / 27M_NSS 13 42 VSS_48 14 41 48M / FSA 15 40 VDD_48 16 39 VTT_PW RGD ...
Page 2
... LVTTL input for enabling assigned SRC clock (active LOW). I 3.3V LVTTL input for enabling assigned SRC clock (active LOW). PWR 3.3V power supply for outputs. GND Ground for outputs 33-MHz clock output O, SE 33-MHz clock output CY28549 Description when VTTPWRGD#/PD is IMFS_C ,V ,V ILFS_C IMFS_C ...
Page 3
... LVTTL input for enabling assigned SRC clock (active LOW). O, DIF True 100-MHz Differential serial reference clocks. O, DIF Complementary 100-MHz Differential serial reference clocks. GND Ground for outputs. O, DIF True 100-MHz Differential serial reference clocks. CY28549 Description DOT96C ...
Page 4
... MHz 100 MHz 33 MHz 27 MHz 100 MHz 33 MHz 27 MHz 100 MHz 33 MHz 27 MHz Description Bit 1 8:2 9 CY28549 Description REF DOT96 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz 14.318 MHz 96 MHz Block Read Protocol Description Start Slave address–7 bits ...
Page 5
... Name RESERVED RESERVED RESERVED RESERVED CY28549 Block Read Protocol Description Acknowledge from slave Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Read = 1 Acknowledge from slave Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave– ...
Page 6
... Disabled Enabled CPU[T/C]0 Output Enable 0 = Disabled Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off Spread on Name PCI4 PCI4 Output Enable 0 = Disabled Enabled PCI3 PCI3 Output Enable 0 = Disabled Enabled PCI2 PCI2 Output Enable 0 = Disabled Enabled CY28549 Description Description Description Description Page ...
Page 7
... Allow control of CPU[T/C]0 with assertion of CPU_STP Free running Stopped with CPU_STP# SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted 1 = Tri-state when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted 1 = Tri-state when CPU_STP# asserted CY28549 Description Description Description Description Page ...
Page 8
... FSA Reflects the value of the FSA pin sampled on power FSA was low during VTT_PWRGD# assertion Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description CY28549 Page ...
Page 9
... Allow control of SRC[T/C]10 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]9 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]8 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED, Set = 0 RESERVED RESERVED RESERVED CY28549 Description Description Description Page ...
Page 10
... PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI2 PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI1 PCI1 (Spread and Non-spread) Output Drive Strength 0 = Low High Name RESERVED RESERVED RESERVED RESERVED RESERVED CY28549 Description Description Description Description Page ...
Page 11
... AT Parallel The CY28549 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28549 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
Page 12
... In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 μs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform when selected for 96 MHz and the SRC waveform when in 100-MHz mode. Figure 4. Power-down Assertion Timing Waveform CY28549 Page ...
Page 13
... CPU_STP# will be stopped within two–six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final state of all stopped CPU clocks is High/Low when driven, Low/Low when tri-stated. Figure 6. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10 ns>200 mV Figure 7. CPU_STP# Deassertion Waveform CY28549 Page ...
Page 14
... PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous ). (See SU manner within two PCI clock periods after PCI_STP# transi- tions to a HIGH level Tsu Figure 9. PCI_STP# Assertion Waveform CY28549 1.8mS 1.8 ms Page ...
Page 15
... Clock Outputs Off Clock VCO Document #:xxx-xxxxx Rev ** PRELIMINARY Tdrive_SRC Tsu Figure 11. PCI_STP# Deassertion Waveform 0.2-0.3mS W ait for Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTTPWRGD# Timing DIagram CY28549 Device is not affected, VTT_PW RGD# is ignored State 3 On Page ...
Page 16
... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – low drive mode per Figure 13 and Figure 15 @133 MHz PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28549 Min. Max. Unit –0.5 4.6 V –0.5 V 4.6 –0 0.5 VDC DD – ...
Page 17
... OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( CY28549 Min. Max. Unit 47.5 52.5 % 71.0 ns – 10 – 500 ps – 300 ppm 9.997001 10.00300 ns 7.497751 7.502251 ns 5 ...
Page 18
... Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V CY28549 Min. Max. – 125 – 125 660 850 –150 – 250 550 – ...
Page 19
... Measurement at 2.4V Measurement at 0.4V Measurement at 1.5V Measurement at 1.5V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from V = 0.175 0.525V OH CY28549 Min. Max. 10.41354 10.47215 OX 10.16354 10.66979 OX 10.16354 10.72266 OX – 125 OX – 300 OX 175 700 – ...
Page 20
... Measurement at 1.5V Measured at crossing point V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28549 Min. Max. – 20 – 125 – 125 660 850 –150 – 250 550 – V HIGH 0.3 – ...
Page 21
... PCI/ USB 60Ω 12Ω 60Ω 12Ω 60Ω 12Ω 60Ω Figure 15. 0.8V Differential Load Configuration CY28549 Measurement Point 5 pF Measurement Point 5 pF Measurement Point easurem ent P oint easurem ent P oint easurem ent P oint ...
Page 22
... Package Type 72-Lead QFN (Punch Version) LF72A 2 C system, provided that the system conforms to the I CY28549 - Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C 51-85216-* Standard Specification Page ...
Page 23
... Document History Page Document Title: CY28549 Clock Generator for Intel Document Number: xxx-xxxxx Orig. of REV. ECN NO. Issue Date Change ** Document #:xxx-xxxxx Rev ** © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...