cy2sstv850oct SpectraLinear Inc, cy2sstv850oct Datasheet
cy2sstv850oct
Related parts for cy2sstv850oct
cy2sstv850oct Summary of contents
Page 1
Features • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:10 differential outputs • External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for EMI reduction ...
Page 2
Pin Description Pin Name 13 CLKINT 14 CLKINC 35 FBINC 36 FBINT 3, 5, 10, 20, 22 YT(0:9) 46, 44, 39, 29, 19, 23 YC(0:9) 47, 43, 40,30,26 32 FBOUTT 33 FBOUTC 12 SCLK I, ...
Page 3
Function Table Inputs AVDD CLKINT GND L GND H 2.5V L 2.5V H Nom Design Nom 2.5V <20 MHz <30 MHZ <20 MHz <30 MHz Power Management The individual output enable/disable CY2SSTV850 allows the user to implement unique power management ...
Page 4
Start Bit Slave Address R/W Data Byte 0 Ack 1 bit 8 bits Table 1. Timing Requirements for the 2-line Serial Interface over Recommended Ranges of Operating Free-air Temperature and VDDI from 3.3V to ...
Page 5
Maximum Ratings Input Voltage Relative to V :...............................V SS Input Voltage Relative DDQ DD Storage Temperature: ................................. –65°C to +150°C Operating Temperature:.................................... 0°C to +70°C Maximum Power Supply: ................................................ 3.5V [5] DC Parameters (AVDD = ...
Page 6
AC Parameters ( DDQ Parameter Description f Operating Clock Frequency CLK t Input Clock Duty Cycle DC t Maximum PLL lock Time lock t /t Output Clocks Slew Rate Output ...
Page 7
Differential Parameter Measurement Information CLKINT CLKINC FBINT FBINC CLKINT CLKINC FBINT FBINC t d( ∅ ) YT[0:9], FBOUTT YC[0:9], FBOUTC YT[0:9], FBOUTT YC[0:9], FBOUTC Rev 1.0, November 21, 2006 t ( ∅ Σ ...
Page 8
... YT[0:9], FBOUTT YC[0:9], FBOUTC YT[0:9], FBOUTT YC[0:9], FBOUTC Figure 6. Differential Signal Using Direct Termination Resistor Ordering Information Part Number CY2SSTV850OC CY2SSTV850OCT CY2SSTV850ZC CY2SSTV850ZCT Rev 1.0, November 21, 2006 t (hper_n jit(hper) hper(n) Figure 4. Half-Period Jitter t c( it(cc) c(n) Figure 5. Cycle-to-Cycle Jitter ...
Page 9
Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package 048 48-Lead Thin Shrunk Small Outline Package, Type mm) Z48 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no ...