cy284108 SpectraLinear Inc, cy284108 Datasheet

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cy284108

Manufacturer Part Number
cy284108
Description
Clock Generator For Intel Blackford And Bayshore Chipsets
Manufacturer
SpectraLinear Inc
Datasheet

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cy284108ZXC
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CY
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Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Features
• Compliant with Intel
• Supports Intel Pentium-4 and Xeon CPUs
• Selectable CPU frequencies
• Four differential CPU clock pairs
• Five 100 MHz Differential SRC clock pairs
• Two buffered Reference Clocks @ 14.31818 MHz
• One 48 MHz USB clock
• Seven 33 MHz PCI clocks
Block Diagram
CPU_STP#
VTT_PWRGD#
PCI_STP#
FS_[C:A]
SDATA
XOUT
SCLK
IREF
XIN
PD
Clock Generator for Intel
PLL1
PLL2
Logic
XTAL
OSC
I
2
C
Network
Divider
®
CK410B
PLL Ref Freq
Tel:(408) 855-0555
USB_48
VDD_REF
REF[0:1]
VDD_CPU
VDD_SRC
VDD_PCI
VDD_PCIF
VDD_48 MHz
CPUT[0:3], CPUC[0:3],
SRCT[0:4], SRCC[0:4]
PCI[0:3]
PCIF[0:2]
®
Blackford and Bayshore Chipsets
• Low-voltage frequency select input
• I
• Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
electromagnetic interference (EMI) reduction
2
CPU
x 4
C™ support with readback capabilities
Pin Configuration
Fax:(408) 855-0550
VDD_SRC
VSS_SRC
VDD_SRC
VDD_SRC
VDD_PCI
VSS_PCI
VSS_PCI
VDD_PCI
USB_48
VDD_48
VSS_48
SRCC0
SRCC1
SRCC2
SRCC3
SRCC4
PCIF_0
PCIF_1
PCIF_2
SRCT0
SRCT1
SRCT2
SRCT3
SRCT4
PCI_0
PCI_1
PCI_2
PCI_3
SRC
x5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCI
x 7
www.SpectraLinear.com
REF
x 2
CY284108
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FSC/TEST_SEL
REF0
REF1
VDD_REF
X1
X2
VSS_REF
FSB/TEST_MODE
FS_A
VDD_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
CPUT2
CPUC2
VDD_CPU
CPUT3
CPUC3
VDDA
VSSA
IREF
NC
VTTPWRGD#**/PD
SDATA
SCLK
Page 1 of 16
USB
x 1

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cy284108 Summary of contents

Page 1

... PCIF[0:2] VSS_48 VDD_SRC VDD_48 MHz SRCT0 SRCC0 USB_48 SRCC1 SRCT1 VSS_SRC SRCT2 SRCC2 SRCC3 SRCT3 VDD_SRC SRCT4 SRCC4 VDD_SRC Tel:(408) 855-0555 Fax:(408) 855-0550 CY284108 PCI REF USB FSC/TEST_SEL 2 55 REF0 REF1 3 54 VDD_REF ...

Page 2

... GND Differential CPU clock outputs PWR 3.3V power supply for outputs GND Ground for outputs PWR 3.3V power supply for outputs GND Ground for outputs PWR 3.3V power supply for outputs GND Ground for outputs – No Connection CY284108 Description Page ...

Page 3

... The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description CY284108 Page ...

Page 4

... Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers CY284108 Page ...

Page 5

... Spread off Spread on Description PCI3 Output Enable 0 = Disable Enable PCI2 Output Enable 0 = Disable Enable PCI1 Output Enable 0 = Disable Enable PCI0 Output Enable 0 = Disable Enable PCIF2 Output Enable 0 = Disable Enable PCIF1 Output Enable 0 = Disable Enable PCIF0 Output Enable 0 = Disable Enable CY284108 Page ...

Page 6

... Driven in power down Tri-state CPU[T/C]0 PD drive mode 0 = Driven in power down Tri-state RESERVED RESERVED RESERVED RESERVED Description RESERVED Stoppable SRC[T/C][4:0] drive mode upon PCI_STP# assertion 0 = Driven in PCI_STOP Tri-state SRC[T/C][4:0] PWRDWN drive mode 0 = Driven in power down Tri-state RESERVED, Set = 0 RESERVED RESERVED RESERVED CY284108 Page ...

Page 7

... FS_B was low during VTT_PWRGD# assertion FS_A Reflects the value of the FS_A pin sampled on power FS_A was low during VTT_PWRGD# assertion Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY284108 Page ...

Page 8

... AT Parallel The CY284108 requires a parallel resonance crystal. Substi- tuting a series resonance crystal will cause the CY284108 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...

Page 9

... After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure example showing the relationship of clocks coming up. Figure 4. Power-down Assertion Timing Waveform Tstable <1.8 ms Tdrive_PWRDN# <300 µs, >200 mV CY284108 Page ...

Page 10

... Rev 1.0, November 22, 2006 Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 6. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay > 0. VDD_A = off Normal Operation VTT_PWRGD# = toggle CY284108 Device is not affected, VTT_PWRGD# is ignored State Sample Inputs straps Wait for <1.8 ms Enable Outputs Page ...

Page 11

... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < Except internal pull-down resistors, 0 < – max. load and freq. per Figure 9 PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY284108 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...

Page 12

... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OL OH Determined as a fraction – T )/( Math averages Figure 9 CY284108 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm ...

Page 13

... Measurement taken from cross point @ 1 µ Measurement taken from cross point @ 10 µ Measurement taken from cross point @ 125 µ Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V CY284108 Min. Max. Unit –150 – mV 210 550 mV – 0.3 V HIGH –0.3 – ...

Page 14

... D iff Ω Ω Figure 9. 0.7V Single-ended Load Configuration CY284108 Measurement Point 5 pF Measurement Point 5 pF Measurement Point 5 pF Measurement Point 5 pF Measurement Point 5 pF ...

Page 15

... SEATING PLANE 0.095 .010 0.110 GAUGE PLANE 0.110 0.008 0°-8° 0.008 0.016 0.0135 CY284108 Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C DIMENSIONS IN INCHES MIN. MAX. 0.005 0.010 0.024 0.040 ...

Page 16

... MAX. 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE CY284108 PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. GAUGE PLANE 0.25[0.010] 0.508[0.020] 0.762[0.030] 0°-8° Page 0.100[0.003] 0.200[0.008] ...

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