cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet
cy28rs600-2
Related parts for cy28rs600-2
cy28rs600-2 Summary of contents
Page 1
... SRCT[0:7] SRCT2 18 SRCC[0:7] SRCC2 19 VSS_SRC 20 VDD_SRC 21 SRCT1 22 SRCC1 23 VDD48 VDD_SRC 24 USB48[1:0] VSS_SRC 25 CLKREQB# 26 ATIGC3 27 ATIGT3 28 56 TSSOP/SSOP Tel:(408) 855-0555 Fax:(408) 855-0550 CY28RS600-2 REF USB_48 VSS_REF 55 FSA_REF0 54 FSB_REF1 53 FSC_REF2 52 RESET_IN# 51 CPU_STOP# 50 CPUT0 49 CPUC0 48 VDD_CPU 47 CPUT1 46 CPUC1 45 CPUT2 44 CPUC2 ...
Page 2
... This may be the POR defaults or a safe value stored in SMBUS registers. I/O, SE 14.318 MHz REF clock output/CPU Frequency Select Intel Type-5 buffer. I/O, SE 14.318 MHz REF clock output/CPU Frequency Select Intel Type-5 buffer. Intel Type-5 buffer. PWR GND for REF, XTAL CY28RS600-2 Description Page ...
Page 3
... Command Code – 8 bits 19 Acknowledge from slave 20 Repeat start 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 Byte Count from slave – 8 bits CY28RS600-2 REF0 USB 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14 ...
Page 4
... Stop Reserved Reserved Reserved SRC[T/C]4 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z Enable CY28RS600-2 Block Read Protocol Description Byte Read Protocol Description Description Page ...
Page 5
... Read Only bit which reflects the value of pin 60 @ VTTPWRGD# assertion SEL1 SEL0 0 0 111.33–167 MHz Frequency Selection Bits CY28RS600-2 Description Description Description ATIG Output N 167–250 100–125 MHz 200–250 166–256 MHz 167–256 Page ...
Page 6
... Free running Stopped with CPU_STP# assertion Reserved Reserved Reserved CLKREQA# Controls SRC0 0 = Not controlled Controlled Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Device ID Bit 3 Device ID Bit 2 Device ID Bit 1 Device ID Bit 0 Reserved Reserved Reserved Reserved CY28RS600-2 Description Description Description Description Page ...
Page 7
... CLKREQC# Controls ATIG1 0 = Not controlled Controlled CLKREQC# Controls ATIG0 0 = Not controlled Controlled Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Smooth switch on/off off Smooth Switch Select 0: Select CPU_PLL (PLL1) 1: Select ATIG_PLL (PLL2) CY28RS600-2 Description Description Description Description Page ...
Page 8
... The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. CY28RS600-2 Description Description Description ...
Page 9
... AT Parallel Crystal Recommendations The CY28RS600-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS600-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a Rev 1.0, November 22, 2006 ADVANCE INFORMATION If Prog_ATIG_EN is set, the values programmed in ATIG_DAF_N[8:0] will be used to determine the ATIG output frequency ...
Page 10
... PD pin or the ramping of the power 1 ) supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 μ deassertion to a voltage greater than CY28RS600-2 Page ...
Page 11
... The safe frequency register is accessible via SMBUS (Bytes 18 & 19). The clock outputs must be stable at the correct safe frequency at least 2 ms before the deassertion of RESET_IN#. CY28RS600-2 Page ...
Page 12
... The maximum latency from the deassertion to active outputs CPU clock cycles. Tdrive_CPU_STP#,10 ns>200 mV Figure 6. CPU_ST0P# Deassertion Waveform S1 VTT_PWRGD# = Low Delay >0. VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28RS600-2 S2 Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
Page 13
... The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0. average over 1-μs duration CY28RS600-2 Min. Max. Unit –0.5 4.6 –0.5 4.6 –0 ...
Page 14
... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 11 Math averages Figure 11 CY28RS600-2 Min. Max. Unit – 300 ppm 9.997001 10.00300 ns OX 7.497751 7.502251 ns OX 5.9982 6.0018 ...
Page 15
... Math averages Figure 11 Math averages Figure 11 See Figure 11. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V@1 μs Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V@10 μs CY28RS600-2 Min. Max. Unit – 0 9.997001 10.00300 ns OX 9.997001 10.05327 ...
Page 16
... ” ” ” ” Figure 11. 0.7V Load Configuration CY28RS600-2 5pF 5pF ...
Page 17
... MAX. 0.20[0.008] 0.05[0.002] 0.17[0.006] 0.15[0.006] SEATING 0.27[0.010] PLANE CY28RS600-2 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C DIMENSIONS IN MM MIN. MAX. REFERENCE JEDEC MO-153 PART # Z6424 STANDARD PKG. ZZ6424 LEAD FREE PKG. GAUGE PLANE 0.25[0.010] ...