cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 10

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CLe
Cs1
Figure 1. Crystal Capacitive Clarification
Total Capacitance (as seen by the crystal)
=
Figure 2. Crystal Loading Example
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
Ci1
Ce = 2 * CL – (Cs + Ci)
Clock Chip
1
XTAL
Ci2
+
X2
1
Ce2
Ce2 + Cs2 + Ci2
INFORMATION
Cs2
1
3 to 6p
ADVANCE
33 pF
Pin
Trim
2.8 pF
Trace
)
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[A:C]# Description
The CLKREQ#[A:C] signals are active LOW inputs used for
clean stopping and starting selected SRC outputs. The
CLKREQ# signal is a de-bounced signal in that it’s state must
remain unchanged during two consecutive rising edges of
DIFC to be recognized as a valid assertion or deassertion.
(The assertion and deassertion of this signal is absolutely
asynchronous.)
CLK_REQ[A:C]# Assertion
The impact of asserting the CLKREQ#[A:C] pins is that all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ#[A:C] are to be stopped after their next
transition. The final state of all stopped DIF signals is Tristate,
both SRCT clock and SRCC clock outputs will be driven
Tristate.
CLK_REQ[A:C]# Deassertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the deassertion to active outputs is between 2 and 6 SRC
clock periods (2 clocks are shown) with all SRC outputs
resuming simultaneously.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must are
held in tristate on the next diff clock# HIGH-to-LOW transition
within four clock periods. Figure 3 and this description are
applicable for all valid CPU frequencies. In the event that PD
mode is desired as the initial power-on state, PD must be
asserted HIGH in less than 10 μs after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 μs of PD deassertion to a voltage greater than
CY28RS600-2
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