cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 8

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Byte 11: WDT System Register
Byte 12: CPU DAF Register1
Byte 13: CPU DAF Register2
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Recovery_Frequency
CPU_DAF_M[6]
CPU_DAF_M[5]
CPU_DAF_M[4]
CPU_DAF_M[3]
CPU_DAF_M[2]
CPU_DAF_M[1]
CPU_DAF_M[0]
CPU_DAF_N[7]
CPU_DAF_N[6]
CPU_DAF_N[5]
CPU_DAF_N[4]
CPU_DAF_N[3]
CPU_DAF_N[2]
CPU_DAF_N[1]
CPU_DAF_N[0]
CPU_DAF_N[8]
WD_TIMER2
WD_TIMER1
WD_TIMER0
Time_Scale
Timer_SEL
WD_Alarm
WD_EN
Name
Name
Name
INFORMATION
ADVANCE
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use HW settings 1: Recovery N[8:0]
Timer_SEL selects the WD reset function at SRESET pin when WD time
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
Time_Scale allows selection of WD time scale
0 = 294 ms
WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp.
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
Watchdog timer enable, when the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
1 = 2.34 s
Description
Description
Description
CY28RS600-2
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