cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet
cy28rs680
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cy28rs680 Summary of contents
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... SRCT5 VDD_SRC_IO SRCC5 SRCT[0:7] SRCT4_SATAT SRCC[0:7] SRCC4_SATAC VSS_SRC VDD_SRC SRCT3 VDD48 SRCC3 48M[0:1] SRCT2 SRCC2 VDD_SRC VSS_SRC ATIGT3 ATIGC3 CLKREQB# Tel:(408) 855-0555 Fax:(408) 855-0550 CY28RS680 ATIG REF USB_48 REF0 2 63 REF1 3 62 REF2 ...
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... PWR 3.3V power supply for SRC outputs GND Ground for SRC outputs O, DIF 100 MHz differential serial reference clock. Intel Type-SR buffer. (10% overclocking support through SMBUS) GND Ground for SRC outputs GND Analog Ground PWR 3.3V Analog Power for PLLs CY28RS680 Description Page ...
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... Selected SRC output is enabled Selected SRC output is disabled. PWR Ground for HyperTransport outputs MHz clock output. Intel Type-5 buffer. PWR 3.3V power supply for HyperTransport outputs I No Connect O, SE 14.318 MHz REF clock output. Intel Type-5 buffer. CY28RS680 Description Page ...
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... Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge 46:39 Data byte 1 from slave – 8 bits 47 Acknowledge 55:48 Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge CY28RS680 Table 2 Page ...
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... SRC[T/C]2 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z Enable Description Reserved Reserved ATIG[T/C]3 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]2 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]1 Output Enable 0 = Disable (Hi-Z Enable ATIG[T/C]0 Output Enable 0 = Disable (Hi-Z Enable CY28RS680 Description Page ...
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... MHz SW Frequency Selection Bits Description CPU(PLL1) Spread Spectrum Selection 00: –0.5% (peak to peak) 01: ±0.25% (peak to peak) 10: –1.0% (peak to peak) 11: ±0.5% (peak to peak) ATIG(PLL2) Spread Spectrum Selection 00: –0.5% (peak to peak) 01: –1.0% (peak to peak) CY28RS680 N 166–250 200–250 166–256 Page ...
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... CLKREQA# Controls SRC0 0 = Not controlled Controlled Description Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Device ID Bit 3 Device ID Bit 2 Device ID Bit 1 Device ID Bit 0 Description Reserved Reserved Reserved Reserved Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28RS680 Page ...
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... Reserved Differential Output Level Setting Diff_VOUT [2:0] 111 = 0.96V 110 = 0.93V 101 = 0.90V default 100 = 0.86V 011 = 0.82V 010 = 0.77V 001 = 0.71V 000 = 0.63V Reserved Smooth switch on/off Off Smooth Switch Select 0 = Select CPU_PLL (PLL1 Select ATIG_PLL (PLL2) CY28RS680 Page ...
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... The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[D:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. CY28RS680 Page ...
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... Enables the setting of CPU_PLL (PLL1) M and N values via byte 15 and Disable Enable Reserved CPU Safe recovery bit 8 for RESET_IN and Watchdog timer timeout. Drive Shunt Cap Motional (max.) (max.) (max 0 0.016 pF CY28RS680 Description Description Description Tolerance Stability Aging (max.) (max.) (max.) 35 ppm 30 ppm 5 ppm Page ...
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... Crystal Recommendations The CY28RS680 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS680 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... Prog_CPU_EN - This bit enables CPU DAF mode. By default not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note: The CPU_DAF_N and M registers must contain valid values before Prog_CPU_EN is set. Default = 0, (No DAF). CY28RS680 Page ...
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... Prog_ATIG_EN is set. Default = 0, (No DAF ATIG_DAF_N - There are eight bits (for 256 values) to linearly change the ATIG frequency (limited by VCO range). Default = Rev 1.0, March 28, 2007 CY28RS680 0, (0000). The allowable values for N are detailed in the frequency select table. Software Frequency Select This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register ...
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... CY28RS680 Page ...
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... NOTE: N[8] bit is hardwired to a logic "1". The SMBus register only requires changes to N[7:0] Rev 1.0, March 28, 2007 M | O(out div) Range of N Fref = 240MHz 167 -250 200 -250 167 -256 Comments Fref = 14.31818MHz CY28RS680 Page ...
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... Measured at crossing point V OX Measured differentially from +150mV Determined as a fraction of 2*(T – T )/( Measured singled-ended, including overshoot Measured singled-ended, including undershoot Measured at crossing point V OX Measured at crossing point CY28RS680 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm 2 7 V/ns ...
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... Measured at 20% and 60% Measured at 1.5V Measured at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V@1 µs Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V@10 µs CY28RS680 Min. Max. Unit 10.12800 9.872001 ns OX 9.872001 10.17827 ns OX – 250 ps OX – 125 ps OX – ...
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... Rev 1.0, March 28, 2007 L1=0.5”, L2=10” L1=0.5”, L2=10” ” ” ” ” Figure 5. Single-ended REF Load Configuration CY28RS680 5pF 5pF Page ...
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... ” ” Figure 7. 0.7V Load Configuration 125 ohms 3900pF 169 ohms 3900pF Figure 8. CPU Output Load Configuration CY28RS680 ...
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... GAUGE PLANE MAX. 0.25[0.010] 0.20[0.008] 0.05[0.002] 0.17[0.006] 0.15[0.006] SEATING 0.27[0.010] PLANE CY28RS680 Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C DIMENSIONS IN MM MIN. MAX. REFERENCE JEDEC MO-153 PART # Z6424 STANDARD PKG. ZZ6424 LEAD FREE PKG. 0.50[0.020] 0.75[0.027] 0.10[0.004] 0° ...