cy28rs680 SpectraLinear Inc, cy28rs680 Datasheet - Page 13

• Manufacturer Part Number: cy28rs680
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, March 28, 2007
CPU_DAF_N - There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default
=0, (0000). The allowable values for N are detailed in the
frequency select table.
CPU_DAF_M - There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
=0. The allowable values for M are detailed in the frequency
select table.
Prog_SRC_EN -This bit enables SRC DAF mode. By default,
it is not set. When set, the operating frequency is determined
by the values entered into the SRC_DAF_N register. Note:
The SRC_DAF_N register must contain valid values before
Prog_SRC_EN is set. Default = 0, (No DAF).
SRC_DAF_N - There are nine bits (for 512 values) to linearly
change the SRC frequency (limited by VCO range). However,
it should be noted that the two MSB are hardwired and only
N[7:0] are required to be program in the SMBus. Default =0,
(0000). The allowable values for N are detailed in the
frequency select table.
Prog_ATIG_EN -This bit enables ATIG DAF mode. By default,
it is not set. When set, the operating frequency is determined
by the values entered into the ATIG_DAF_N register. Note:
The SRC_DAF_N register must contain valid values before
Prog_ATIG_EN is set. Default = 0, (No DAF
ATIG_DAF_N - There are eight bits (for 256 values) to linearly
change the ATIG frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register. FSEL - There are three bits (for 8 combina-
tions) to select predetermined CPU frequencies from a table.
The table selections are detailed in.
Smooth Switching
The device contains one smooth switch circuit, which is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 µs. The frequency
overshoot and undershoot will be less than 2%.
The smooth switch circuit can be assigned auto or manual
mode. In auto mode, the clock generator will assign smooth
switch automatically when the PLL will perform overclocking.
For manual mode, the smooth switch circuit can be assigned
to either PLL via SMBUS. By default the smooth switch circuit
is set to auto mode. Either PLL can still be overclocked when
it does not have control of the smooth switch circuit, but it is
not guaranteed to transition to the new frequency without large
frequency glitches.
Note: Do not enable overclocking and change the N values of both PLLs in the
same SMBUS block write and use smooth switch mechanism on spread
spectrum on/of
f.
CY28RS680
Page 13 of 20