cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 6

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Byte 4: Spread Spectrum Control Register
Byte 5: System Configuration Register
Byte 6: Revision and Device ID
Byte 7: Vendor ID
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
@Pup
@Pup
@Pup
@Pup
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
ATIG_SS_OFF
SRC_SS_OFF
CLKREQA#
ATIG_SS0
CPU_SS1
CPU_SS0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USB48
Name
Name
Name
CPU2
CPU1
CPU0
Name
REF
INFORMATION
ADVANCE
Reserved
Reserved
Reserved
Reserved
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Device ID Bit 3
Device ID Bit 2
Device ID Bit 1
Device ID Bit 0
CPU (PLL1) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: ±0.25% (peak to peak)
10: –1.0% (peak to peak)
11: ±0.5% (peak to peak)
ATIG (PLL2) Spread Spectrum Selection
00: –0.5% (peak to peak)
01: –1.0% (peak to peak)
ATIG_PLL (PLL2) Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
SRC_PLL (PLL3) Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
USB48 Output Drive Strength
0 = 1x, 1 = 2x
Reserved
REF Output Drive Strength
0 = 1X, 1 = 2x
Allow control of CPU2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP# assertion
Allow control of CPU1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP# assertion
Allow control of CPU0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP# assertion
CLKREQA# Controls SRC0
0 = Not controlled, 1 = Controlled
Reserved
Reserved
Reserved
Reserved
Description
Description
Description
Description
CY28RS600-2
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