cy28rs600-2 SpectraLinear Inc, cy28rs600-2 Datasheet - Page 12

• Manufacturer Part Number: cy28rs600-2
• Description: Clock Generator For Ati Rs5xx, 6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
CPU_ST0P# Assertion
The CPU_ST0P# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_ST0P# pin is asserted, all CPU outputs that
are set with the SMBus configuration to be stoppable via
assertion of CPU_ST0P# will be stopped within two and six
CPU clock periods after being sampled by two rising edges of
the internal CPUC clock. The final states of the stopped CPU
signals are CPUT = HIGH and CPUC = LOW. There is no
CPUC Internal
CPUT Internal
VDD_A = 2.0V
CPU_STP#
CPU_STP#
CPUT
CPUC
Power Off
CPUT
CPUC
S0
Figure 7. Clock Generator Power-up/Run State Diagram
Figure 6. CPU_ST0P# Deassertion Waveform
Figure 5. CPU_ST0P# Assertion Waveform
INFORMATION
VDD_A = off
ADVANCE
>0.25 ms
Tdrive_CPU_STP#,10 ns>200 mV
Delay
S1
VTT_PWRGD# = toggle
VTT_PWRGD# = Low
change to the output drive current values during the stopped
state.
CPU_ST0P# Deassertion
The deassertion of the CPU_ST0P# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is 2 to 6 CPU clock cycles.
Operation
Normal
S3
Inputs straps
Sample
Enable Outputs
S2
Wait for <1.8ms
CY28RS600-2
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