cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 8

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
Byte 6 Control Register 6
Byte 7 Control Register 7
Byte 8 Vendor ID
Byte 9 Control Register 9
Bit
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
HW
HW
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
outputs except those set to
PCI, PCIF and SRC clock
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
SRC[T/C][9:1]
TEST_MODE
RESEREVD
free running
TEST_SEL
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Name
Name
Name
REF0
FSC
FSB
FSA
PRELIMINARY
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
RESERVED
REF0 Output Drive Strength
0 = Low, 1 = High
SW PCI_STP Function
0 = SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Description
Description
CY28549
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