cy28443oxc-3t SpectraLinear Inc, cy28443oxc-3t Datasheet - Page 14

• Manufacturer Part Number: cy28443oxc-3t
• Description: Clock Generator Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 20, 2006
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
CPU_STOP#
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
SRC 100MHz
DOT96C
DOT96T
PCI_STP#
DOT96T
DOT96C
PD
PCI_F
PD
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 10. PCI_STP# Assertion Waveform
Tsu
SU
). (See
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
CY28443-3
1.8 ms
1.8 ms
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