cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet - Page 14

• Manufacturer Part Number: cy8c3446lti-075es2
• Description: Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
• Manufacturer: Cypress Semiconductor Corporation.

17. LVD and Comparator Interrupt Level
18. UDB Low Power Retention
January 7, 2011
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PROBLEM DEFINITION
The LVD and comparator interrupts only support level trigger mode. Setting the LVD and comparator interrupt
modes to edge mode has no effect. See the PSoC 3: CY8C34 Family Technical Reference Manual for details.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
NA
SCOPE OF IMPACT
An LVD or comparator interrupt keeps interrupts pending, because they are level triggered, until the LVD or
comparator output changes to the inactive state.
WORKAROUND
The LVD and comparator signals are routed out to GPIOs through the
brought back in as GPIO interrupts, which are edge triggered.
FIX STATUS
Silicon revision fix confirmed in production silicon.
PROBLEM DEFINITION
When the device enters a low power mode (sleep or hibernate), the following register values are not retained.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
Entering one of the device low power modes while using a UDB based component.
SCOPE OF IMPACT
The register values are not retained upon wakeup. The UDB based component will not function in the same
manner as prior to entering the low power mode.
WORKAROUND
Preserve each of the registers value by storing in SRAM prior to entering a low power mode. Upon wakeup,
restore register values to proper location. Because component placement can change between each build,
Cypress recommends using the component #defines located in the component.h file, rather than absolute
register names. In the following example, preserve and restore PWM_1_COMPARE1_LSB.
#define PWM_1_COMPARE1_LSB
FIX STATUS
Silicon revision fix confirmed in production silicon. Workaround for ES2 fix available in PSoC Creator Beta 5.
• UDB[00..15]_D0
• UDB[00..15]_D1
• UDB[00..15]_CTL
• UDB[00..15]_MSK
• UDB[00..15]_ACTL
Document Number: 001-61136 Rev. *C
Errata Document
(*(reg8 *) PWM_1_PWMUDB_sP8_pwmdp_u0__D0_REG)
PSoC
Digital System Interconnect (DSI)
®
3: CY8C34 Family
and
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