cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet - Page 8

• Manufacturer Part Number: cy8c3446lti-075es2
• Description: Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
• Manufacturer: Cypress Semiconductor Corporation.

January 7, 2011
4. Brown Out
5. Delta Sigma ADC Range
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PROBLEM DEFINITION
The brown out detection circuit on ES2 silicon does not function properly and is unable to guarantee brown
out detection in both active and sleep power modes.
TRIGGER CONDITIONS
Vcca, Vccd, Vdda, Vddd voltage below 1.71 V.
SCOPE OF IMPACT
The device will reset on a brown out condition, but the brown out threshold may be too low to guarantee device
function. Device state and data retention are not guaranteed which may result in improper code execution and
device function.
WORKAROUND
There are several possible workarounds. These workarounds are not required for prototyping at room
temperature (25 C).
1. Externally guarantee that all supply voltages do not fall below 1.8 V when regulated and 1.71 V when
2. Provide external voltage monitoring circuitry to reset the device in the event that Vdda or Vddd drop below
3. Use the Low Voltage Interrupt (LVI) setting LVI_A/D_SEL[3:0] = 0001b for 1.95 V or higher voltage to
FIX STATUS
Silicon revision fix confirmed in production silicon.
PROBLEM DEFINITION
When using the Delta Sigma ADC, the maximum useable input into the ADC is 90% of the reference value.
PARAMETERS AFFECTED
NA
TRIGGER CONDITIONS
Using the Delta Sigma ADC.
SCOPE OF IMPACT
An input into the ADC greater than 90% of the reference value results in increased noise, which produces
inaccurate results.
WORKAROUND
There are two possible workarounds.
1. If possible, increase external reference voltage so that the input voltage does not exceed 90% of
2. Attenuate the input signal so that it never exceeds 90% of the reference value
FIX STATUS
Silicon revision fix confirmed in ES2 with date code 1026 or later in conjunction with PSoC Creator Beta 5
release.
unregulated. If operating in sleep mode, use a Schottky diode to clamp Vdda to Vcca by connecting the
diode cathode to Vdda
1.8 V when regulated and 1.71 V when unregulated. One possible implementation for regulated mode is
to use a 2.2 V supervisor device. In unregulated mode, there is insufficient margin to use a voltage
monitoring circuit to implement this workaround. If JTAG interface is enabled, the workaround will not reset
the device and may not be used
detect that the Vdda and Vddd supplies have dropped below the threshold. Ensure sufficient bulk
capacitance to guarantee that the CPU can service the interrupt and perform a hardware reset. Hardware
reset is performed by writing 0x00 to register RESET_IPOR_CR0 (0x46F0). In unregulated mode, there
is insufficient margin to use the LVI 1.701 voltage detection level to implement this workaround
reference value
Document Number: 001-61136 Rev. *C
Errata Document
PSoC
®
3: CY8C34 Family
8
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