cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet - Page 19

• Manufacturer Part Number: cy8c3446lti-075es2
• Description: Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
• Manufacturer: Cypress Semiconductor Corporation.

27. Configurable XRES Pin
28. 68-Pin QFN Boost Circuit
January 7, 2011
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PROBLEM DEFINITION
When reading the NV Latches, the CNVL_XRESMEN bit glitches to ‘0’, thus resetting the device if the
configurable XRES pin is enabled.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
Reading the status of the XRES NVL.
SCOPE OF IMPACT
None.
WORKAROUND
Two workarounds are available:
1. For 100-pin and 68-pin devices, do not use the Configurable XRES pin, only use the dedicated XRES pin.
2. For 48-pin devices, always configure the GPIO XRES pin P1[2] to pull-up drive mode before reading the
FIX STATUS
Silicon revision fix confirmed in production silicon.
PROBLEM DEFINITION
The 68-pin QFN package of ES2 devices have Vbat and Vboost shorted together.
TRIGGER CONDITION(S)
None.
SCOPE OF IMPACT
Vboost circuit does not function and supply will be shorted if Vbat is connected to GND and Vboost is
connected to supply voltage.
WORKAROUND
Do not use the Vboost feature of the chip and ground both Vbat and Vboost as detailed in Section 2 of the
CY8C34 family datasheet.
FIX STATUS
Silicon revision fix confirmed in ES2 with date code 1026 or later.
The dedicated XRES pin is not affected by reads of the CNVL_XRESMEN bit
XRES NVL bit using the spc_nvl_read command. This is done by writing 0x05 to PRT1_PC2 register
(0x500A). This will apply a 5 k pull-up to the pin, which may have an effect on circuitry attached to the
pin. PSoC Creator Beta 3 implements the required workaround when programming the device
Document Number: 001-61136 Rev. *C
Errata Document
PSoC
®
3: CY8C34 Family
19
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