cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet - Page 18

• Manufacturer Part Number: cy8c3446lti-075es2
• Description: Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
• Manufacturer: Cypress Semiconductor Corporation.

25. SWO Pin
26. JTAG/SWD XRES Requirement
January 7, 2011
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PROBLEM DEFINITION
When the device is configured with Single Wire Debug (SWD) as the debug port, P1[3] is automatically
configured for SWO and cannot be used as a GPIO.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
Configuring the device to use SWD as the debug port.
SCOPE OF IMPACT
Unable to use P1[3] as a GPIO.
WORKAROUND
NA
FIX STATUS
Silicon revision fix confirmed in production silicon.
PROBLEM DEFINITION
Device reset cannot be done through the JTAG/SWD interface.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
Attempts to execute a software reset through the JTAG/SWD interface.
SCOPE OF IMPACT
NA
WORKAROUND
Two workarounds are available:
1. For 100-pin and 68-pin devices, do not use the Configurable XRES pin, only use the dedicated XRES pin.
2. For 48 pin devices, always configure the GPIO XRES pin P1[2] to pull-up drive mode before reading the
FIX STATUS
Silicon revision fix confirmed in production silicon.
The dedicated XRES pin is not affected by reads of the CNVL_XRESMEN bit.
XRES NVL bit using the spc_nvl_read command. This is done by writing 0x05 to PRT1_PC2 register
(0x500 A). This will apply a 5 kO pull-up to the pin, which may have an effect on circuitry attached to the
pin. PSoC Creator Beta 3 implements the required workaround when programming the device.
Document Number: 001-61136 Rev. *C
Errata Document
PSoC
®
3: CY8C34 Family
18
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