cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet - Page 24

• Manufacturer Part Number: cy8c3446lti-075es2
• Description: Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
• Manufacturer: Cypress Semiconductor Corporation.

37. SIO Increased Current Consumption
January 7, 2011
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PROBLEM DEFINITION
Each SIO pin may cause up to an additional 1 mA of Vddio current in some use cases.
PARAMETERS AFFECTED
NA
TRIGGER CONDITION(S)
If an SIO pin’s voltage exceeds its Vddio supply by 0.5 V, the trigger condition is set (region 1). After the trigger
condition is set, the SIO pin causes increased current when its voltage is between Vss + 0.5 V and Vddio –
0.5 V (region 2). The trigger condition is reset when the SIO pin is brought within the range of Vss to Vss +
0.5 V (region 3). The trigger condition may unknowningly be met during device powerup due to differences in
supply ramps.
SCOPE OF IMPACT
Up to 1 mA of additional current per SIO is possible on the SIO pin’s Vddio supply when in the high current
region after the trigger condition is met. No additional Vddio current will occur when not in the high current
region even if the trigger condition is met. No other features of the SIO pin are impacted.
WORKAROUND
There are three workarounds available:
1. If trigger condition cannot occur based on system design then no action is required
2. If trigger condition can occur in the system:
FIX STATUS
Silicon revision fix confirmed in production silicon.
a) If increased Vddio current is acceptable no action is required
b) If the SIO pin is used as a digital input or output that will only quickly transition through the high current
c) If the SIO pin must operate in the high current region after the trigger condition is met, no direct
region, then no action is required. Higher current is seen during the brief transition period through the
high current region from high to low logic levels if the trigger condition is met
workaround is available and increased current is seen. If the SIO can be brought back between Vss
and Vss+0.5 V, the trigger condition can be reset until the pin retriggers the condition. The SIO can
be brought back to Vss by setting the pin to a low logic level by using API, DMA, or hardware. This
will minimize the duration of the extra Vddio current
Vddio + 0.5 V
Vddio - 0.5 V
Document Number: 001-61136 Rev. *C
Vss + 0.5V
Errata Document
Vddio
5.5 V
Vss
High Current Region if Triggered (2)
Trigger Set Region (1)
Reset Region (3)
PSoC
®
3: CY8C34 Family
24
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