mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 106

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Caches
data cache is disabled for the second half of the operand. Internal accesses always bypass
the instruction and data caches while CDIS is recognized, and the contents of the caches
are unchanged. Disabling the caches with CDIS does not affect snoop operations. CDIS is
intended primarily for use by in-circuit emulators to allow swapping between the tags and
emulator memories.
The privileged CINV and CPUSH instructions support cache management, by selectively
pushing and/or invalidating an individual cache line, a full page, or an entire cache, for either
or both instruction and data caches. CINV allows selective invalidation of cache entries. The
CPUSH instruction will either push and invalidate all matching lines, or push and leave the
line valid, depending on the state of the DPI bit of the CACR register. (Note that only CPUSH
instructions which specify the data cache are affected by the DPI bit. Since the instruction
cache cannot have dirty data, a CPUSH specifying the instruction cache is interpreted as a
CINV instruction.) Because of the size of the caches, pushing pages or an entire cache may
incur a significant time penalty. Therefore, the CPUSH instruction may be interrupted to
avoid large interrupt latencies. The state of the CDIS signal or the cache enable or no-allo-
cate bits in the CACR does not affect the operation of CINV and CPUSH.
5.4 CACHING MODES
Every cache access has an associated caching mode from the MMU that determines how
the cache handles the access. An access can be cachable in either the writethrough or
copyback modes, or it can be cache inhibited in precise or imprecise modes. The CM field
(from the transparent translation register (TTR) or MMU translation table page descriptor)
corresponding to the logical address of the access normally specifies, on a page-by-page
basis, one of these caching modes. When the cache is enabled and memory management
is disabled, the default caching mode is writethrough.
The MMU provides the cache mode user page attributes (UPAx) and write protection for
each access. This information may come from a TTR which matches or from the MMU trans-
lation tables via the ATC. If both the TTR and the ATC match the access, the TTR provides
the information. If the paging MMU is disabled (TCR bit clear) and neither TTR matches,
then the cache mode, UPAx, and write protection will be that which is specified in the default
bits of the TCR. After reset, the defaults are writethrough cache mode, UPAx bits are zero,
and all addresses may be written.
The TTRs and MMUs allow the defaults to be overridden. In addition, some instructions and
integer unit operations perform data accesses that have an implicit caching mode associ-
ated with them. The following paragraphs discuss the different caching accesses and their
related cache modes.
5.4.1 Cachable Accesses
If the CM field of a page descriptor, TTR, or default field of the TCR indicates writethrough
or copyback, then the access is cachable. A read access to a writethrough or copyback page
is read from the cache if matching data is found. Otherwise, the data is read from memory
and used to update the cache. Since instruction cache accesses are always reads, the
selection of writethrough or copyback modes do not affect them. The following paragraphs
describe the writethrough and copyback modes in detail.
MOTOROLA
M68060 USER’S MANUAL
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