mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 190

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

7.8.1.1 INTERRUPT ACKNOWLEDGE CYCLE (TERMINATED NORMALLY). When the
MC68060 processes an interrupt exception, it performs an interrupt acknowledge bus cycle
to obtain the vector number that contains the starting location of the interrupt exception han-
dler. Some interrupting devices have programmable vector registers that contain the inter-
rupt vectors for the exception handlers they use. Other interrupting conditions or devices
cannot supply a vector number and use the autovector bus cycle described in 7.8.1.2
Autovector Interrupt Acknowledge Cycle.
The interrupt acknowledge bus cycle is a read transfer. It differs from a normal read cycle in
the following respects:
The responding device places the vector number on the lower byte of the data bus during
the interrupt acknowledge bus cycle, and the cycle is terminated normally with TA. Figure 7-
27 and Figure 7-28 illustrate a flowchart and functional timing diagram for an interrupt
acknowledge cycle terminated with TA.
Note that the acknowledge termination ignore state capability is applicable to the interrupt
acknowledge cycle. If enabled, TA and other acknowledge termination signals are ignored
for a user-programmed number of BCLK cycles.
7.8.1.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When
device cannot supply a vector number, it requests an automatically generated vector
(autovector). Instead of placing a vector number on the data bus and asserting TA, the
device asserts the autovector (AVEC) signal with TA to terminate the cycle. AVEC is only
sampled with TA asserted. AVEC can be grounded if all interrupt requests are autovectored.
The vector number supplied in an autovector operation is derived from the interrupt priority
level of the current interrupt. When the AVEC signal is asserted with TA during an interrupt
acknowledge bus cycle, the MC68060 ignores the state of the data bus and internally gen-
erates the vector number, which is the sum of the interrupt priority level plus 24 ($18). There
are seven distinct autovectors that can be used, corresponding to the seven levels of inter-
rupts available with IPLx signals. Figure 7-29 illustrates a functional timing diagram for an
autovector operation.
Note that the acknowledge termination ignore state capability is applicable to the interrupt
acknowledge cycle. If enabled, AVEC and other acknowledge termination signals are
ignored for a user-programmed number of BCLK cycles.
7.8.1.3 SPURIOUS INTERRUPT ACKNOWLEDGE CYCLE. When a device does not
respond to an interrupt acknowledge bus cycle, spurious with TA, or AVEC and TA, the
external logic typically returns the transfer error acknowledge signal (TEA). In this case, the
MC68060 automatically generates the spurious interrupt vector number 24 ($18) instead of
the interrupt vector number. If operating in the MC68040 acknowledge termination mode,
MOTOROLA
• TT1 and TT0 = $3 to indicate an acknowledged bus cycle
• Address signals A31–A0 are set to all ones ($FFFFFFFF)
• TM2–TM0 are set to the interrupt request level (the inverted values of IPLx).
M68060 USER’S MANUAL
the
Bus Operation
interrupting
7-35