mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 306

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Instruction Execution Timing
nation operand can be routed to the sOEP before the actual “execution” of the pOEP instruc-
tion. The test succeeds in this example.
10.2 TIMING ASSUMPTIONS
For the timing data presented, the following assumptions are made:
10-10
1. The data presents the execution times for individual instructions and makes no as-
2. The OEP is loaded with the opword and all required extension words at the beginning
3. The OEP does not experience any sequence-related pipeline stalls. The most com-
as a base register for address calculation with no stall, or as an index register for
The MC68060 provides another change/use optimization for a commonly encountered
sumptions concerning the ability of the MC68060 to dispatch multiple instructions in a
given machine cycle. For sequences where instruction-pairs are dispatched, the exe-
cution time of the two instructions is defined by the execution time of the instruction in
the pOEP.
of each instruction execution. This implies that the OEP spends no time waiting for the
instruction fetch pipeline (IFP) to supply opwords and/or extensions.
mon example of this type of stall is a “change/use” register stall. This type of stall re-
sults from a register being modified by an instruction and a subsequent instruction
generating an address using the previously modified register. The second instruction
must stall in the OEP until the register is actually updated by the previous instruction.
For example:
address calculation with no stall, if Xi.l*{1,4}. If the index register used is Xi.l*2, Xi.l*8,
or Xi.w, then the previously described 3 cycle stall occurs.
construct—when an address register is loaded from memory and then used in an oper-
and address calculation, the OEP experiences a one cycle stall.
In this sequence, the second instruction is held for 2 clock cycles stalling for the first
instruction to complete the update of the d0 register. If consecutive instructions load
a register and then use that register as the base for an address calculation (An), a 2-
clock-cycle wait may be incurred. This represents the maximum change/use penalty
for a base register. The maximum change/use penalty for an index register (Xi) is 3
clock cycles (for Xi.l*2, Xi.l*8, and Xi.w). The change/use penalty for an index register
if Xi.l*1 or Xi.l*4 is 2 clock cycles.
Certain instructions have been optimized to ensure no change/use stall occurs on
subsequent instructions. The destination register of the following instructions is avail-
able for subsequent instructions:
muls.l #<data>,d0
mov.l (a0,d0.l*4),d1
lea
mov.l&imm,Rn
movq
clr.lDn,
any op(An)+
any op–(An)
M68060 USER’S MANUAL
MOTOROLA