mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 74

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mc68ec060

Manufacturer Part Number
mc68ec060
Description
Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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FITC—1/2-Cache Mode (Instruction ATC)
DCO—Default Cache Mode (Data Cache)
DUO—Default UPA bits (Data Cache)
DWO—Default Write Protect (Data Cache)
DCI—Default Cache Mode (Instruction Cache)
DUI—Default UPA Bits (Instruction Cache)
Bit 0—Reserved by Motorola. Always read as zero.
MOTOROLA
These bits are two user-defined bits for operand accesses (see 4.2.2.3 Descriptor Field
Definitions ).
These bits are two user-defined bits for instruction prefetch bus cycles (see 4.2.2.3
Descriptor Field Definitions )
0 = The instruction ATC operates with 64 entries.
1 = The instruction ATC operates with 32 entries.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
0 = Reads and writes are allowed.
1 = Reads are allowed, writes cause a protection exception.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
M68060 USER’S MANUAL
Memory Management Unit
4-5

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